Charge Trap Bi-Layer for Memory Cell Leakage and Retention
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Solution Overview
Problem
Current non-volatile memory technologies, such as Flash memory, face challenges in scaling with new semiconductor processes, leading to reduced data retention and increased leakage, while seeking to balance cost, yield, and performance.
Innovation Solution
A memory cell system is developed with a charge-storage bi-layer comprising a silicon-rich nitride charge trap layer and a regular silicon nitride intermediate layer, sandwiched between a first and second insulator layer, which improves programming and erasing performance and data retention by enhancing charge-trapping efficiency and inhibiting gate leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon content in the nitride layer is increased to improve charge-trapping efficiency, then programming and erasing performance improve, but leakage characteristics worsen
Solution Approach 1:
The nitride layer is segmented into two distinct layers: a silicon-rich nitride charge trap layer (5-20 nm thick with 60-80 at% silicon) for charge storage, and a silicon-poor nitride intermediate layer (2-10 nm thick with 20-40 at% silicon) for leakage suppression. This segmentation allows each layer to be optimized for its specific function, resolving the contradiction between charge-trapping efficiency and leakage characteristics.
2Productivity
If Flash memory is scaled with new semiconductor processes to increase density, then data storage capacity increases, but data retention decreases
Solution Approach 1:
Different regions of the nitride structure are assigned different silicon concentrations to perform different functions: the bottom charge trap layer uses high silicon content (60-80 at%) for efficient charge storage enabling high density, while the top intermediate layer uses low silicon content (20-40 at%) for leakage suppression ensuring data retention. This local quality differentiation allows simultaneous achievement of high density and retention.
3Manufacturing precision
If nitride layer thickness is reduced to improve scalability, then manufacturing precision improves, but data retention worsens
Solution Approach 1:
Rather than using a single thin nitride layer that compromises retention, the structure is segmented into two thinner layers whose combined thickness is reduced for scalability. The charge trap layer (5-20 nm) provides charge storage while the intermediate layer (2-10 nm) prevents leakage, allowing the total nitride thickness to be reduced while maintaining or improving data retention through the synergistic interaction between layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The bi-layer configuration enhances erase and programming performance by approximately three orders of magnitude and increases data retention compared to silicon-rich nitride or nitride alone, while maintaining a larger memory window and improved retention behavior despite reduced nitride thickness.
Implementation Method 1
the charge is trapped in the nitride layer
Implementation Method 2
improving programming and erasing performance and data retention by enhancing charge-trapping efficiency and inhibiting gate leakage
Data Source
AI summary
A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.