Charge Trap Flash Memory Pre-Programming for Data Retention
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Solution Overview
Problem
In charge trap flash memory devices, the lateral movement of charges due to electrostatic attraction forces between memory cells leads to reduced data retention, as the distribution of threshold voltages becomes scattered during the erasing operation, causing data loss over time.
Innovation Solution
A method involving pre-programming memory cells with a negative effective verifying voltage to achieve a narrower distribution of threshold voltages, ensuring that the pre-programmed state has threshold voltages less than 0V, thereby reducing lateral movement of charges and improving data retention. This involves applying a pre-programming voltage and verifying the state using a negative effective verifying voltage until the memory cell meets the desired programmed state, and then erasing the previously programmed state before pre-programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the erasing operation is performed in a block unit, then all data in the block is erased, but the threshold voltage distribution becomes highly scattered and cannot be controlled
Solution Approach 1:
The patent segments the erasing operation into two distinct phases: a fast block-level erasure that removes all data efficiently, followed by a precise page-level verification that controls and narrows the threshold voltage distribution. This segmentation allows the system to benefit from both high-speed block erasure and precise distribution control.
Solution Approach 2:
The patent performs a preliminary block erasure operation to clear all data quickly, then follows up with a verification step that acts as a preliminary refinement. This preliminary action removes the bulk of charges, and the subsequent verification narrows the distribution, combining speed and precision.
2Quantity of substance
If memory cell size is reduced, then storage capacity increases, but coupling between memory cells increases making threshold voltage control difficult
Solution Approach 1:
The patent implements a feedback mechanism where the threshold voltage distribution is verified after erasure, and based on this verification, additional verification voltages are applied to further narrow the distribution. This feedback loop continuously monitors and adjusts the threshold voltage distribution to achieve the desired control precision.
Solution Approach 2:
The patent changes the verification voltage parameter dynamically - applying an initial verification voltage after block erasure, then applying additional verification voltages based on the measured threshold voltage distribution. This parameter adjustment allows precise control of the threshold voltage distribution regardless of memory cell size.
3Reliability
If charges are stored in the charge trap layer, then data is retained, but charges move laterally between adjacent memory cells due to electrostatic attraction
Solution Approach 1:
The patent applies preliminary anti-action by performing a block erasure operation that removes charges from the charge trap layer before they can move laterally. By clearing the charges proactively, the system prevents the electrostatic attraction that would cause lateral movement and data loss during retention.
Solution Approach 2:
The patent converts the potential harm of charge accumulation into benefit by using the block erasure operation. The same erasure mechanism that clears data is used to remove charges that would otherwise cause lateral movement, transforming a data-loss operation into a data-protection mechanism.
4Manufacturing precision
If incremental step pulse programming is used, then threshold voltage distribution is reduced for MLC, but programming complexity increases
Solution Approach 1:
The patent extracts the threshold voltage distribution control function from the programming operation itself and places it in a separate verification operation performed after block erasure. This separation allows the programming to remain simple while the verification independently handles the distribution control, reducing overall programming complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the lateral movement of charges, maintaining data integrity by minimizing the movement of electrons between memory cells, thus enhancing the data retention property of charge trap flash memory devices.
Implementation Method 1
In CTF memory devices, since the charges are trapped in the insulating layer having the charge trap site such as the silicon nitride Si3N4
Implementation Method 2
the lateral movement of charges, which may be caused by an electrostatic attraction force of the charges stored in memory cells
Implementation Method 3
electrons may be injected into the memory cell, on which the selected bit line and the selected word line overlap each other, through a tunneling oxide layer
Implementation Method 4
holes may be injected into the charge trap layer from the active region through the tunneling oxide layer, to neutralize and erase the electrons stored in the memory cells
Data Source
AI summary
Provided is a method and device for reducing lateral movement of charges. The method may include pre-programming at least one memory cell that is in an erased state by applying a pre-programming voltage to the at least one memory cell to have a narrower distribution of threshold voltages than the at least one erased state memory cell and verifying that the pre-programmed memory cell is in the pre-programmed state using a negative effective verifying voltage.