Charge Trap Flash Memory Data Retention Verification
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Solution Overview
Problem
Charge trap flash memory devices face data retention failures due to electric charge loss from the silicon nitride charge trapping layer, leading to a gradual lowering of threshold voltage and increased risk of misinterpretation during read operations.
Innovation Solution
Implementing a method that includes programming memory cells with a program voltage, verifying using a first program verify voltage, and reprogramming if necessary using incremental step pulse programming to ensure threshold voltage is above a retention read level, thereby preventing data retention failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electric charges are injected into the silicon nitride charge trapping layer to program the memory cell, then the memory cell can store data, but the electric charges may be lost through the tunneling layer or blocking layer causing data retention failure
Solution Approach 1:
The patent applies preliminary action by performing a retention verify operation after the program operation to check whether the memory cell maintains sufficient threshold voltage. If the retention verify fails, the patent then performs a re-program operation before the read operation. This preliminary verification and corrective action prevents data retention failures by ensuring charges are properly trapped before data is read.
2Ease of operation
If the threshold voltage of the memory cell is lowered to enable reading, then read operations can be performed, but the threshold voltage may drop below the read line voltage causing misinterpretation of data
Solution Approach 1:
The patent implements feedback through the retention verify operation that checks the threshold voltage after programming. The system uses the read line voltage as a reference to determine whether the threshold voltage has dropped too low. This feedback mechanism ensures that only memory cells with sufficient threshold voltage are considered to have successfully stored data, preventing misinterpretation during read operations.
3Reliability
If a retention verify operation is added to check data retention, then data retention reliability is improved, but the operation time and complexity increase
Solution Approach 1:
The patent applies partial action by performing the retention verify operation only when necessary - specifically after program operations and before read operations. The retention verify uses a simplified check at a predetermined threshold voltage level rather than a comprehensive analysis, balancing thoroughness with efficiency. This partial verification approach ensures data retention reliability while minimizing the time added to the overall operation sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures data retention by maintaining a sufficient threshold voltage, reducing the likelihood of data retention failures and allowing for efficient operation of charge trap flash memory devices.
Implementation Method 1
a tunneling layer 110 is formed over a substrate 100... Hot electrons from the substrate 100 are trapped in trap sites inside the charge trapping layer 120
Implementation Method 2
a silicon nitride film used as a charge trapping layer 120... traps capable of trapping electric charges therein
Data Source
AI summary
A charge trap flash memory device is capable of preventing a data retention fail by ensuring a data retention margin. A method for operating the charge trap flash memory device is provided. A selected memory cell is programmed using a program voltage. The selected memory cell is verified using a first program verify voltage. Date retention states of selected memory cell having passed the program verify step are verified using a retention verify voltage. A read step of determining a program pass or fail by reading data of the selected memory cell having passed the retention verify step is performed using a read voltage.


