Charge-Trap Memory Cell With Buried Channel for Fast Erase
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing non-volatile memory cells, particularly eSTM memory cells, suffer from inefficiencies in programming and erasing operations, and existing methods fail to address these issues effectively.
Innovation Solution
A transistor comprising a doped well of a first conductivity type and a transistor with a buried doped channel, a gate stack, and a vertical gate structure that facilitates efficient programming and erasing operations, utilizing a method for controlling the memory cell, the transistor comprising a doped second conductivity type and a gate stack, and a vertical gate structure that facilitates efficient programming and erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional eSTM memory cell structure is used, then the memory cell can store data non-volatily, but the programming and erasing operations are slow and power-consuming
Solution Approach 1:
The gate structure is segmented into multiple independent gates (first gate, second gate, third gate) that can be controlled separately. This segmentation allows selective activation of gates during programming and erasing operations, enabling faster charge injection and removal while reducing overall power consumption by activating only the necessary gates for each operation.
Solution Approach 2:
The invention transitions from a planar gate structure to a three-dimensional configuration with gates positioned at different vertical levels and orientations. The first gate is positioned above the channel, the second gate is below the channel, and the third gate is vertically oriented. This multi-dimensional arrangement creates multiple pathways for charge injection and extraction, significantly improving programming and erasing speeds while distributing power consumption across multiple gate control lines.
2Ease of manufacture
If the memory cell structure is simplified, then manufacturing becomes easier, but programming and erasing efficiency decreases
Solution Approach 1:
The memory cell structure incorporates multiple gates that serve dual purposes: the first and second gates work together for programming operations, while the second and third gates collaborate for erasing operations. This multi-functional design allows a single cell structure to perform both programming and erasing with high efficiency without requiring separate dedicated structures for each operation, maintaining manufacturing simplicity while achieving high productivity.
3Productivity
If existing control methods are used, then the memory cell can be operated, but programming and erasing operations are inefficient
Solution Approach 1:
The control method applies preliminary voltage to the appropriate gate before the actual programming or erasing operation. During programming, voltage is pre-applied to the first gate to prepare the channel for charge injection. During erasing, voltage is pre-applied to the third gate to prepare for charge extraction. This preliminary action reduces the time required for the actual data writing and erasing operations by ensuring the electric field is already established when the main operation begins.
Solution Approach 2:
The control method employs periodic voltage pulses applied to different gates in a specific sequence. During programming, voltage pulses are alternately applied to the first and second gates to progressively inject charges into the floating gate. During erasing, similar periodic pulsing is applied to the second and third gates for efficient charge removal. This periodic action breaks down the programming and erasing processes into manageable stages, significantly reducing total operation time compared to continuous voltage application.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed memory cell structure allows for faster and more efficient programming and erasing operations, with reduced power consumption and improved reliability compared to existing eSTM memory cells.
Implementation Method 1
The gate stack comprises a first layer adapted to trap charges
Implementation Method 2
a current flowing through the buried doped channel so that hot carriers are generated in the buried doped channel
Implementation Method 3
an electric field between the doped well and the third conductive layer injects the generated hot carriers having a first polarity inside the first layer
Data Source
AI summary
The present disclosure relates to a memory cell (1) and to a method of erasing the memory cell (1). The memory cell comprises a doped well (100) of a first conductivity type and a transistor (T). Transistor (T) comprises a doped first region (106) of a second conductivity type opposite to the first conductivity type, the first doped region extending in the doped well (100); a buried doped channel (118) of the second conductivity type extending in the doped well (100); and a gate stack (108) resting on the doped well (100), above the buried doped channel (118). The gate stack (108) comprises a first layer (110) adapted to trap charges, a second insulating layer (112) resting on the first layer and a third conductive layer (114) resting on the second layer.