Charge Trap Memory Gate Stack With Segmented Silicon Nitride Layers
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Solution Overview
Problem
Current non-volatile memory technologies, such as Flash memory, face challenges in scaling with new semiconductor processes, leading to reduced data retention, increased manufacturing costs, and inefficiencies in programming and erasing performance due to the limitations of floating gate and charge trapping architectures, particularly with silicon content in nitride layers.
Innovation Solution
A memory cell system is developed with a charge trap layer over a semiconductor substrate, protected by a protection layer and a protection enclosure, which includes a silicon-rich nitride charge trap layer and insulating layers to enhance data retention and reduce manufacturing complexities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon content in the nitride layer is increased to improve charge-trapping efficiency, then programming and erasing performance is improved, but data retention deteriorates due to poor leakage characteristics
Solution Approach 1:
The charge trap layer is divided into multiple distinct layers: a first charge trap layer with higher silicon content (improved charge-trapping efficiency) and a second charge trap layer with lower silicon content (improved data retention). This segmentation allows each layer to optimize for its specific function, resolving the contradiction between programming performance and data retention.
2Productivity
If new semiconductor processes are used to scale Flash memories, then manufacturing capability is improved, but data retention deteriorates due to reduction of key feature sizes
Solution Approach 1:
The patent changes the compositional parameters of the charge trap layer by using multiple layers with different silicon contents. This allows the structure to maintain data retention performance even when scaled using new semiconductor processes, as the multi-layer design provides a buffer against feature size reduction effects.
3Reliability
If interface between charge trapping layer and blocking oxide layers is optimized, then leakage characteristics are improved, but manufacturing complexity increases due to additional process steps
Solution Approach 1:
The patent forms the charge trap layers between the tunneling oxide and blocking oxide layers in advance, before subsequent processing steps. This preliminary action ensures proper interface formation and leakage characteristics while integrating smoothly into the existing manufacturing flow, minimizing additional process complexity.
Data Source
AI summary
A memory system is provided including forming a memory gate stack having a charge trap layer over a semiconductor substrate, forming a protection layer to cover the memory gate stack, and forming a protection enclosure for the charge trap layer with the protection layer and the memory gate stack.