Charge-Trap Memory Device High-K Blocking Layer
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Solution Overview
Problem
Conventional charge-trap type non-volatile memory devices face issues with defective erase operations due to horizontal movement of electrical charges in the silicon nitride layer and breakdown voltage drop caused by damage to the blocking insulating layer during dry-etching, leading to reduced reliability.
Innovation Solution
A method of forming a non-volatile memory device with a tunnel insulating layer, a charge-trap layer, and a blocking insulating layer, where the blocking insulating layer is made of a material with a higher dielectric constant than silicon oxide and the gate electrode is made of a material with a higher work function than polysilicon, along with the use of spacers to protect the sidewalls during etching, ensuring complete discharge of charges and maintaining the integrity of the blocking insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional SONOS memory device uses silicon oxide for both blocking insulating layer and tunnel-insulating layer, then the device structure is simple, but charge trapped in the charge-trap layer cannot be completely discharged during erase operation due to same dielectric constants causing back tunneling
Solution Approach 1:
The patent changes the dielectric constant parameter of the blocking insulating layer by using a high-dielectric material (such as tantalum oxide, hafnium oxide, or barium strontium titanate) with a dielectric constant greater than that of silicon oxide. This parameter change creates a dielectric constant difference between the blocking insulating layer and tunnel-insulating layer, which prevents back tunneling during erase operation and enables complete discharge of trapped charges, thereby resolving the contradiction between structural simplicity and erase operation completeness.
2Reliability
If the gate electrode is made of material with higher work function than polysilicon, then defective erase operation is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent changes the work function parameter of the gate electrode by using materials such as tungsten, titanium nitride, or tantalum nitride, which have higher work functions than polysilicon. This parameter change reduces defective erase operations by preventing unwanted charge injection from the gate electrode into the charge-trap layer, thereby improving reliability while the added material complexity is offset by the use of standard semiconductor manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of charge-trap type non-volatile memory devices by reducing charge leakage, preventing breakdown voltage drops, and minimizing defective erase operations, thereby improving overall device performance.
Implementation Method 1
dielectric constants of the two layers may be the same, and thus almost the same electric field may be provided at the two insulating layers, causing back tunneling
Implementation Method 2
the blocking insulating layer may be damaged by a plasma generated during dry-etching
Data Source
AI summary
Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate.