Charge Trap Memory Integration with Logic CMOS via Segmentation
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Solution Overview
Problem
The integration of non-volatile charge trap memory devices with logic CMOS devices is challenging due to compatibility issues in fabrication processes, such as interference between logic MOS gate oxide processes and memory device dielectric stacks, and the need for high voltage operation which conventional logic device processes do not support.
Innovation Solution
A non-volatile charge trap memory device is integrated with logic devices by forming a SONOS dielectric stack after logic MOS well and channel implants, using a multi-layered liner to offset HV MOS source and drain, and employing nitridation to improve dielectric stack quality, while avoiding silicidation of the memory device to reduce stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If logic MOS gate oxide process is integrated with memory device dielectric stack fabrication, then system-on-a-chip functionality is achieved, but fabrication process compatibility is compromised
Solution Approach 1:
The substrate is divided into distinct first and second regions, with the first region dedicated to memory device dielectric stack formation and the second region to logic MOS gate oxide processing. This spatial segmentation allows each region to undergo specialized fabrication processes without interfering with the other, enabling both memory and logic functionality on the same chip while maintaining process compatibility.
Solution Approach 2:
Different regions of the substrate are assigned different dielectric structures tailored to their specific functional requirements. The first region receives a memory-optimized dielectric stack with specific thickness and material composition, while the second region receives a logic-optimized gate oxide layer. This local customization allows each region to achieve optimal performance for its intended purpose.
2Adaptability or versatility
If channel and well implant processing is performed for logic devices, then logic device functionality is achieved, but memory device dielectric stack is degraded
Solution Approach 1:
The substrate is segmented into distinct processing zones where the first region containing the memory dielectric stack is spatially separated from the second region where logic device implants are performed. This segmentation prevents implant ions from damaging the memory dielectric stack while still enabling necessary logic device channel and well implantation in the isolated second region.
3Productivity
If silicided contacts are formed for logic transistor, then logic device performance is improved, but nonvolatile charge trap memory device is adversely affected
Solution Approach 1:
The substrate is divided into a first region for memory devices and a second region for logic devices. Silicided contacts are formed only in the second logic device region, allowing logic transistors to benefit from reduced contact resistance and improved performance, while the first region memory devices remain unaffected by the silicidation process.
4Ease of operation
If high voltage is applied for memory device operation, then memory function is achieved, but logic device breakdown voltage is exceeded
Solution Approach 1:
The integrated circuit is divided into separate first and second regions, allowing independent voltage domain management. The first region can operate at high voltages required for memory device programming and erasing operations, while the second logic device region maintains its standard low-voltage operation, preventing breakdown and ensuring reliable operation of both device types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes disruption to the charge trap dielectric stack, enhances data retention, and allows for high voltage operation without degrading the memory device, improving the reliability and performance of the integrated memory and logic devices.
Implementation Method 1
employing nitridation to improve dielectric stack quality
Data Source
AI summary
An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.