Charge Trap Memory Integration with Logic CMOS
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Solution Overview
Problem
The integration of non-volatile charge trap memory devices with logic CMOS devices in system-on-a-chip architecture is challenging due to compatibility issues in fabrication processes, such as interference between logic MOS gate oxide and memory device dielectric stacks, and the need for high voltage operation which conventional logic device processes are not optimized for.
Innovation Solution
A non-volatile charge trap memory device is integrated with logic devices by forming a SONOS dielectric stack before logic MOS gate oxidation, using a multi-layered liner to offset HV MOS source and drain, and avoiding silicidation of the memory device to reduce stress, while allowing HV operation through extended source and drain implants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If logic MOS gate oxide process is integrated with memory device dielectric stack fabrication, then system-on-a-chip functionality is achieved, but fabrication process compatibility deteriorates
Solution Approach 1:
The patent divides the substrate into distinct first and second regions, with the first region dedicated to non-volatile memory devices and the second region to logic devices. This spatial segmentation allows each region to be optimized for its specific fabrication requirements, enabling integration of dissimilar devices while maintaining process compatibility.
Solution Approach 2:
The patent applies different fabrication processes to different regions: the first region receives processes optimized for memory devices (forming dielectric stacks, avoiding silicidation), while the second region receives processes optimized for logic devices (MOS gate oxide, silicided contacts). This local quality approach allows each region to have the specific properties needed for its device type.
2Adaptability or versatility
If channel and well implant processing is performed for logic devices, then logic device functionality is achieved, but memory device dielectric stack integrity deteriorates
Solution Approach 1:
The substrate is segmented into a first region for memory devices and a second region for logic devices. Channel and well implant processing is applied selectively only to the second region, protecting the dielectric stack in the first region from damage while enabling logic device functionality.
Solution Approach 2:
The patent uses region-specific processing as an intermediary mechanism to prevent harmful interactions. By controlling which processes are applied to which regions, the dielectric stack in the first region is protected from the damaging effects of channel and well implant processing while still allowing logic devices in the second region to function properly.
3Productivity
If silicided contacts are formed for logic transistors, then logic device performance is improved, but nonvolatile charge trap memory device performance deteriorates
Solution Approach 1:
The patent applies silicided contacts selectively only to the second region containing logic devices, where they improve performance. The first region containing nonvolatile charge trap memory devices is excluded from silicidation, preserving their performance while enabling logic device optimization.
Solution Approach 2:
Different contact treatments are applied to different regions: silicided contacts are formed in the second region for logic devices to enhance performance, while the first region maintains non-silicided contacts suitable for memory device operation. This local differentiation resolves the performance conflict.
4Ease of manufacture
If conventional low voltage logic device processes are used, then manufacturing simplicity is maintained, but high voltage operation capability deteriorates
Solution Approach 1:
The patent divides the logic device region into first and second subsets, with the first subset optimized for low voltage operation using conventional processes, and the second subset optimized for high voltage operation with extended source and drain implants. This segmentation allows high voltage capability without requiring all logic devices to use complex high voltage processes.
Solution Approach 2:
Different voltage optimization strategies are applied to different subsets of logic devices: the first subset uses conventional low voltage processes for manufacturing simplicity, while the second subset uses extended source and drain implants to achieve high voltage operation capability where needed.
Data Source
AI summary
A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.