Charge Trap Memory Integration with Resistors and Capacitors
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Solution Overview
Problem
The integration of non-volatile charge trap memory devices with resistors and capacitors in semiconductor devices becomes increasingly challenging as they scale to smaller dimensions and higher densities, leading to higher costs and complexity due to the need for more patterning operations and new materials, such as high-k materials and metal gate layers.
Innovation Solution
A method is described where the charge trapping dielectric stack is patterned to expose portions of resistors and capacitors in peripheral regions, allowing for the formation of these devices while minimizing the number of patterning operations, by selectively removing dielectric layers from non-array regions, thereby reducing unnecessary capacitance and simplifying the process flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If non-volatile charge trap memory devices are integrated with resistors and capacitors using conventional fabrication methods, then functional integration is achieved, but the number of patterning operations increases and fabrication complexity increases
Solution Approach 1:
The patent merges the fabrication processes for charge trap memory devices with resistors and capacitors into a unified flow. The charge trapping dielectric stack is formed over the entire substrate including peripheral regions, and a single patterning operation defines memory cell regions, resistor regions, and capacitor regions simultaneously. This combining of previously separate fabrication sequences reduces the total number of patterning operations while achieving full functional integration.
Solution Approach 2:
The charge trapping dielectric stack serves multiple functions: it provides charge trapping capability for memory cells in array regions, and simultaneously serves as an insulating layer for resistors and capacitors in peripheral regions. This multi-functional use of the same dielectric structure eliminates the need for separate insulating layers and reduces fabrication complexity.
2Quantity of substance
If new materials such as high-k materials and metal gate layers are introduced to scale devices to smaller dimensions, then device density increases, but fabrication cost and process complexity increase
Solution Approach 1:
The patent uses uniform silicon nitride dielectric material throughout the charge trapping dielectric stack across the entire substrate, including both array and peripheral regions. This homogeneous material selection avoids the complexity of integrating multiple new materials (high-k materials, metal gates) while still achieving the required device density through optimized device geometry and layout in the peripheral regions.
Solution Approach 2:
The substrate is segmented into array regions and peripheral regions, with the charge trapping dielectric stack selectively patterned in array regions and retained in peripheral regions. This segmentation allows different device types (memory cells, resistors, capacitors) to coexist on the same substrate using the same base materials, simplifying the fabrication process while maintaining high device density.
Data Source
AI summary
A semiconductor device structure and method to form the same. The semiconductor device structure includes a non-volatile charge trap memory device and a resistor or capacitor. A dielectric layer of a charge trap dielectric stack of the memory device is patterned to expose a portion of a first conductive layer peripheral to the memory device. A second conductive layer formed over the dielectric layer and on the exposed portion of the first conductive layer is patterned to form resistor or capacitor contacts and capacitor plates.