Charge-Trap Vertical Memory Cell Structure for Capacitor-Free Scaling
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Solution Overview
Problem
Dynamic random-access memory (DRAM) devices face limitations in high integration due to the difficulty in reducing capacitor capacitance, which restricts their ability to achieve high capacity and compactness.
Innovation Solution
A capacitorless semiconductor memory device design featuring a semiconductor substrate with a common source semiconductor layer, insulating layers, word line structures, and memory cell dielectric layers that include a gate insulating layer and a charge trap layer, allowing for high integration without the need for capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor is used in DRAM device, then memory function can be achieved, but high integration is limited due to difficulty in reducing capacitor capacitance
Solution Approach 1:
The patent removes the capacitor component entirely from the memory device structure. Instead of using a capacitor to store charge, the invention employs a charge trap layer that can trap and retain charges directly within the memory cell structure, thereby achieving memory functionality without the need for separate capacitor components and enabling higher integration density
Solution Approach 2:
The patent changes the fundamental operating mechanism from capacitor-based charge storage to charge trap layer-based charge retention. By modifying the physical mechanism from electrostatic field storage in a capacitor to charge trapping in a dielectric layer, the invention achieves both memory functionality and reduced structural complexity for higher integration
2Device complexity
If capacitor size is reduced to achieve high integration, then integration density improves, but memory function becomes difficult to maintain
Solution Approach 1:
By extracting the capacitor from the memory cell structure and replacing it with a charge trap layer integrated into the semiconductor substrate, the invention maintains memory functionality without requiring large capacitor components, thus achieving high integration density while preserving reliable memory operation
Solution Approach 2:
The patent uses a composite structure consisting of the charge trap layer (which may be a high-k dielectric material) combined with the semiconductor substrate and doped regions. This composite approach enables effective charge trapping and retention within a compact structure, maintaining memory function at high integration densities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high integration and capacity in semiconductor memory devices by eliminating the need for capacitors, enhancing retention time and memory window characteristics through thyristor structures and charge trapping mechanisms.
Implementation Method 1
a charge trap layer arranged between the gate insulating layer and the channel layer
Implementation Method 2
a common source semiconductor layer doped with impurities of a first conductivity type and arranged on the semiconductor substrate
Implementation Method 3
the drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type
Data Source
AI summary
A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.