Charge Trap Memory Device Segmentation for Data Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Highly integrated charge trap-type non-volatile semiconductor memory devices face challenges with reliability and programming time due to small threshold voltage margins and electron leakage, which affect data storage and retrieval efficiency.
Innovation Solution
Implementing a 3-level charge trap region configuration with two charge trap regions operating in pairs to store three bits of data, using distinct threshold voltage groups and a data control circuit to manage programming and reading operations, thereby enhancing integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a charge trap-type non-volatile memory device uses a simplified manufacturing process compared to floating gate-type devices, then manufacturing ease is improved, but threshold voltage margins become small leading to reliability degradation
Solution Approach 1:
The invention divides the charge trap region into two separate charge trap regions (first charge trap region and second charge trap region) within a single memory element. Each charge trap region can be independently programmed and read, allowing for multi-level data storage. This segmentation enables larger threshold voltage margins by distributing charge storage across multiple regions, thereby improving reliability while maintaining manufacturing simplicity.
2Quantity of substance
If two charge trap regions are used to store data in two threshold voltage groups, then data storage capacity is improved, but programming time increases due to sequential operations
Solution Approach 1:
The invention implements a periodic action by performing read operations alternately on the first and second charge trap regions during the programming process. Instead of completing all programming operations on one region before moving to the next, the method periodically switches between regions, verifying data storage status at intermediate stages. This periodic verification and switching approach optimizes programming time by preventing redundant operations and enabling early termination when programming is complete.
3Loss of information
If electron injection is performed into the nitride film for data programming, then data storage is achieved, but electron leakage occurs affecting data retention
Solution Approach 1:
By segmenting the charge storage function across two distinct charge trap regions, the invention reduces the burden on each individual region. Each region handles a portion of the data storage responsibility, which reduces the density of stored charges per region and consequently minimizes electron leakage effects. This segmentation strategy improves data retention reliability while maintaining overall data storage capability.
Solution Approach 2:
The invention applies local quality by enabling independent programming and reading of each charge trap region. Each region can be optimized for specific data bits (e.g., first region for MSB, second region for LSB), allowing tailored charge injection strategies that minimize leakage. The selective reading capability also enables verification of data integrity in each region, improving overall data retention through localized quality control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3-level charge trap region configuration improves data storage capacity, reliability, and reduces programming time by utilizing larger threshold voltage intervals and efficient data bit mapping, allowing for high-speed programming and reading operations.
Implementation Method 1
Channel Hot-Electron injection (CHE) can be used as an electron injection method
Data Source
AI summary
Disclosed herein is a charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same. The charge trap-type 3-level non-volatile semiconductor memory device includes a memory array including a plurality of memory elements, each capable of storing data in at least two charge trap regions depending on the direction of current flow, and a page buffer driven to map three data bits to threshold voltage groups of the two charge trap regions. The charge trap-type non-volatile semiconductor memory device has charge trap regions each storing 1.5 bits of data. That is, a single memory element has charge trap regions for storing 3 bits of data, thereby improving device integration while maintaining a high operating speed during programming and reading operations.