3D Charge Trap Memory Stack Isolation for Data Retention
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Solution Overview
Problem
Three-dimensional nonvolatile memory devices face challenges in improving operational reliability due to the limitations of two-dimensional structures, particularly in maintaining data retention and reducing interference between stacked memory cells.
Innovation Solution
A semiconductor device with a gate stack structure featuring alternately stacked interlayer insulating and conductive layers, including a channel structure with blocking insulating and charge trap layers, where the sidewalls of the interlayer insulating layers protrude to isolate memory structures, reducing interference between adjacent memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are stacked vertically in a three-dimensional structure, then the degree of integration is improved, but interference between adjacent memory cells increases
Solution Approach 1:
The patent divides the continuous charge trap layer into separate segments by introducing blocking insulating layers between adjacent memory cells. This segmentation prevents electrical interference between cells while maintaining vertical stacking for high integration. The blocking insulating layers act as electrical isolators that segment the charge trap regions of neighboring cells.
Solution Approach 2:
The blocking insulating layers serve as intermediary elements between adjacent charge trap layers. These intermediary blocking layers physically and electrically separate the charge trap regions of neighboring memory cells, preventing direct interference while allowing both cells to function within the same vertical stack structure.
2Quantity of substance
If charge trap layers are positioned closer to increase density, then storage capacity is improved, but data retention reliability deteriorates
Solution Approach 1:
By segmenting the charge trap layers with blocking insulating layers, the patent enables closer positioning of charge trap regions while preventing charge leakage between adjacent cells. This segmentation allows higher storage capacity through increased density without sacrificing data retention reliability, as each segmented charge trap region remains electrically isolated.
Solution Approach 2:
The blocking insulating layers are positioned beforehand between charge trap layers to prevent potential charge interference. This prior cushioning with insulating material ensures that even when charge trap layers are positioned closely for high density, charge leakage is prevented, thereby maintaining data retention reliability.
3Object-generated harmful factors
If blocking insulating layers are added to isolate memory cells, then interference is reduced, but device complexity increases
Solution Approach 1:
The blocking insulating layers are merged with the interlayer insulating layers that already exist in the three-dimensional memory structure. By combining the isolation function with existing structural elements, the patent reduces interference between memory cells without significantly increasing device complexity. The blocking layers utilize the same material deposition processes and structural framework as the interlayer insulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data retention and reduces interference between memory cells, improving the operational reliability and efficiency of three-dimensional nonvolatile memory devices by physically and electrically spacing charge trap layers apart.
Implementation Method 1
forming blocking insulating layers by oxidizing the sidewalls of the second material layers, which are exposed through the recess regions
Data Source
AI summary
There are provided a semiconductor device and a manufacturing method of a semiconductor device. The semiconductor device includes: a gate stack structure including interlayer insulating layers and conductive layers, which are alternately stacked; a channel structure extending in a vertical direction in the gate stack structure; and memory structures interposed between the conductive layers and the channel structure. Each of the memory structures includes a blocking insulating layer and a charge trap layer, which are sequentially formed on a sidewall of each of the conductive layers. Sidewalls of the interlayer insulating layers, which are in contact with the channel structure, are located on the same line as a sidewall of the charge trap layer, which is in contact with the channel structure, or side portions of the interlayer insulating layers, which are in contact with the channel structure, further protrude as compared with the sidewall of the charge trap layer.