Charge-Trapping Gate Stack Fabrication in CMOS Flow
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Solution Overview
Problem
Conventional CMOS process flows for fabricating MOSFETs are incompatible with the formation of charge-trapping gate stacks, leading to degradation of non-volatile memory devices due to differences in material composition and processing conditions.
Innovation Solution
A method is developed to integrate a charge-trapping gate stack into the CMOS flow by forming a dielectric stack with a tunneling dielectric and a charge-trapping layer, followed by the deposition of cap layers and patterning to create a gate stack, where an oxidation process forms a blocking oxide, consuming the cap layers and optimizing the gate-oxide formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional CMOS process flows are used to fabricate MOSFETs, then MOSFET fabrication is achieved, but the formation of charge-trapping gate stacks is incompatible and degrades non-volatile memory device performance
Solution Approach 1:
The process is divided into separate sequence: first forming the charge-trapping gate stack (tunneling dielectric, charge-trapping layer, blocking oxide) before fabricating the MOSFET gate oxide. This segmentation prevents the MOSFET gate-oxide formation process from degrading the memory device's ONO stack, as each structure is formed in an optimized sequence rather than simultaneously conflicting processes.
Solution Approach 2:
The charge-trapping gate stack is formed preliminarily before the MOSFET gate oxide is created. By establishing the memory device structure first with its sensitive ONO stack, then subsequently forming the MOSFET gate oxide around it, the patent ensures the memory structure is already in place and protected from degradation during the MOSFET oxidation process.
2Ease of manufacture
If materials and processes for ONO stack formation are used, then charge-trapping gate stack is formed, but these processes differ significantly from standard CMOS and detrimentally impact MOSFET fabrication
Solution Approach 1:
The patent merges the formation of the charge-trapping gate stack with the CMOS fabrication sequence by integrating the ONO stack formation steps into the overall process flow. The tunneling dielectric, charge-trapping layer, and blocking oxide are formed using sequences that can be coordinated with standard CMOS steps, reducing the need for entirely separate process lines.
Solution Approach 2:
The fabrication sequence is designed to serve multiple functions: forming the charge-trapping gate stack for non-volatile memory while simultaneously preparing the structure for subsequent MOSFET gate oxide formation. The process achieves dual compatibility by creating a unified sequence that supports both memory device integrity and MOSFET fabrication requirements.
3Reliability
If MOSFET gate-oxide or dielectric is formed, then MOSFET function is ensured, but performance of previously formed ONO stack is significantly degraded by altering thickness or composition
Solution Approach 1:
Instead of forming the MOSFET gate oxide first and then attempting to add the charge-trapping gate stack, the patent inverts the sequence: the charge-trapping gate stack (ONO structure) is formed first, and then the MOSFET gate oxide is formed around it. This inversion prevents the oxidation process from altering the ONO stack's thickness or composition, as the ONO stack is already in place and the subsequent oxidation is controlled to affect only the MOSFET regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the successful integration of non-volatile memory devices with charge-trapping gate stacks into CMOS flows, enhancing the performance and compatibility of MOSFETs and memory devices by maintaining the integrity of the ONO stack.
Implementation Method 1
an oxidation process performed to form a blocking oxide over the charge-trapping layer, in which the oxidation process consumes the first cap layer
Data Source
AI summary
A method of fabricating a memory device is described. Generally, the method includes forming a channel from a semiconducting material overlying a surface of a substrate, and forming dielectric stack on the channel. A first cap layer is formed over the dielectric stack, and a second cap layer including a nitride formed over the first cap layer. The first and second cap layers and the dielectric stack are then patterned to form a gate stack of a device. The second cap layer is removed and an oxidation process performed to form a blocking oxide over the dielectric stack, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.