Charge-Trapping Gate Stack Integration in CMOS Flow
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Solution Overview
Problem
The integration of charge-trapping gate stacks into CMOS flows is challenging due to differences in material composition and processing methods, which can degrade the performance of MOSFETs by altering the thickness or composition of the charge-trapping layer.
Innovation Solution
A method involving the formation of a dielectric stack with a tunneling dielectric, a multi-layer charge-trapping layer, and a cap layer, followed by an oxidation process to form a blocking oxide, which consumes the cap layer and a portion of the charge-trapping layer, while simultaneously forming a gate oxide, is employed to integrate non-volatile memory devices with MOSFETs in a CMOS flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If charge-trapping gate stack formation processes are integrated into standard CMOS process flow, then non-volatile memory devices can be included in integrated circuits, but the performance of MOSFETs deteriorates due to alterations in gate oxide thickness or composition
Solution Approach 1:
The process is divided into separate regions: a first region for forming charge-trapping gate stacks with nitride/oxynitride layers, and a second region for forming MOSFETs with gate oxides. This spatial segmentation allows each device type to be fabricated with optimized processes without mutual interference, resolving the contradiction between integration capability and MOSFET performance
Solution Approach 2:
Different material compositions and processing conditions are applied to different regions: the charge-trapping region uses nitride/oxynitride dielectrics with specific nitrogen content, while the MOSFET region uses standard gate oxide materials. This local differentiation enables each region to maintain its required performance characteristics while being part of the same integrated circuit
2Ease of manufacture
If gate oxide or dielectric is formed to complete MOSFET fabrication, then MOSFET functionality is achieved, but the performance of previously formed charge-trapping gate stack degrades due to altered thickness or composition of the charge-trapping layer
Solution Approach 1:
The charge-trapping gate stack is formed completely with its nitride/oxynitride dielectric layers before any gate oxide formation occurs in the MOSFET region. This preliminary completion of the charge-trapping structure prevents subsequent gate oxide processes from altering its thickness or composition, maintaining manufacturing precision while allowing MOSFET fabrication to proceed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the successful integration of non-volatile memory devices with MOSFETs, maintaining the performance of both by controlling the thickness and composition of the charge-trapping layer and forming a blocking oxide that enhances device functionality.
Implementation Method 1
an oxidation process to form a blocking oxide overlying the charge-trapping layer
Implementation Method 2
a tunneling dielectric overlying the surface of the substrate
Data Source
AI summary
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.