Charge-Trapping Memory Cells for In-Array IMPLY Logic
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Solution Overview
Problem
Conventional computing configurations face power loss and increased footprint due to long bus wires between memory and logic devices, which degrades CPU performance and requires significant additional logic circuitry for in-memory computing.
Innovation Solution
Implementing charge-trapping devices as both memory cells and logic circuitry through IMPLY operations within the cells, reducing the integrated circuit footprint by integrating logic functions directly into the memory portion of the IC memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard logic functionality is incorporated within electronic memory through in-memory computing, then data processing capability is improved, but device complexity increases due to additional logic circuitry requirements
Solution Approach 1:
The patent merges memory and logic functions into a single integrated structure by implementing logical operations (AND, OR, NOT, NAND, NOR, XOR, XNOR) directly within the memory cell array using charge-trapping devices. This eliminates the need for separate logic circuitry, thereby improving data processing capability while reducing device complexity.
Solution Approach 2:
The memory cells are designed to perform multiple functions: they can store data and simultaneously execute logical operations. The charge-trapping devices serve dual purposes as both storage elements and logic gates, enabling the memory array to function as a universal computing unit that can perform various logical operations without additional dedicated circuitry.
2Productivity
If additional logic circuitry is added for in-memory computing, then data processing capability is improved, but integrated circuit footprint increases
Solution Approach 1:
By combining memory storage and logic processing into the same physical space within the memory cell array, the patent eliminates the need for separate logic circuit blocks. This integration dramatically reduces the integrated circuit footprint while maintaining full data processing capability, as the same transistors and charge-trapping structures serve both storage and computation functions.
3Speed
If long bus wires are used between memory and logic devices, then data transfer capability is maintained, but power loss increases and CPU performance degrades
Solution Approach 1:
The patent extracts the logic processing function from separate logic devices and relocates it directly into the memory array. This eliminates the need for long bus wires connecting memory to external logic units, thereby removing the source of power loss while preserving data transfer capability through direct in-array processing.
Data Source
AI summary
Some embodiments relate to an integrated circuit including first and second charge-trapping devices and a control circuit. The first charge-trapping device includes a first charge-trapping structure arranged over a substrate between a first gate structure and a first channel region. The second charge-trapping device is coupled in series with the first charge-trapping device and includes a second charge-trapping structure arranged over the substrate between a second gate structure and a second channel region. The control circuit is coupled to the first and second gate structures and is configured to store a first input of an IMPLY operation as a stored value of the first charge-trapping device, store a second input of the IMPLY operation as a stored value of the second charge-trapping device, and update the stored value of the second charge-trapping device based on the stored value of the first charge-trapping device to perform the IMPLY operation.