Charge-Trapping Layer Deposition Without a Low-Temperature Seed Layer
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Solution Overview
Problem
Existing methods for preparing charge-trapping layers on silicon-on-insulator substrates are time-consuming and require a low-temperature seed layer formation, limiting production efficiency without compromising quality.
Innovation Solution
A process involving a single-crystal silicon base substrate with low resistivity is introduced into a deposition chamber, where an intrinsic silicon epitaxial layer is formed, followed by a dielectric layer, and then a polycrystalline silicon charge-trapping layer is formed at a higher temperature, with minimal exposure to a carrier gas between these steps to maintain surface conditions, allowing rapid growth without a low-temperature seed layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a low-temperature seed layer formation step is used to form the charge-trapping layer, then the quality of the trapping layer is maintained, but the production time increases and manufacturing efficiency decreases
Solution Approach 1:
The invention extracts and removes the low-temperature seed layer formation step from the conventional process. By directly forming the charge-trapping layer at high temperature (1000-1200°C) on the dielectric layer without a separate seed layer step, the process eliminates the time-consuming low-temperature formation step while maintaining layer quality through the dielectric layer's surface properties and in-situ deposition conditions
Solution Approach 2:
The invention changes the deposition temperature parameter from conventional low-temperature (below 1010°C) to high temperature (1000-1200°C). This parameter change enables direct formation of the charge-trapping layer with appropriate crystallinity and quality, eliminating the need for a separate low-temperature seed layer step and thereby improving production efficiency
2Productivity
If the charge-trapping layer is formed at high temperature, then the growth rate increases and production efficiency improves, but the base substrate may deform preventing assembly by molecular adhesion
Solution Approach 1:
The invention segments the structure by introducing a dielectric layer between the base substrate and the charge-trapping layer. This dielectric layer acts as a buffer that decouples the thermal effects, allowing the charge-trapping layer to be formed at high temperature (1000-1200°C) for rapid growth while the dielectric layer protects the base substrate from excessive thermal deformation, maintaining assembly compatibility
Solution Approach 2:
The dielectric layer serves as an intermediary layer that mediates between the high-temperature charge-trapping layer formation process and the base substrate. It provides thermal isolation and mechanical buffering, enabling high-temperature deposition without causing unacceptable deformation to the base substrate, thus allowing both high growth rate and substrate integrity
3Adaptability or versatility
If the base substrate is removed from the chamber between steps, then process flexibility increases, but the manufacturing time increases and productivity decreases
Solution Approach 1:
The invention merges multiple process steps into a single continuous in-situ sequence within the same deposition chamber. The dielectric layer formation and charge-trapping layer formation are combined in one uninterrupted process flow, eliminating the need to remove and re-introduce the base substrate between steps. This reduces manufacturing time and improves productivity while maintaining process control and flexibility through sequential gas phase deposition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a high-quality charge-trapping layer at a significantly higher growth rate, improving production efficiency while maintaining radiofrequency performance and reducing deformation, with a second harmonic distortion measurement below -70 dB.
Implementation Method 1
forming an intrinsic silicon epitaxial layer on the base substrate by introducing into the chamber a precursor gas containing silicon
Implementation Method 2
forming a dielectric layer on an exposed face of the intrinsic silicon epitaxial layer by introducing a reactive gas into the chamber
Implementation Method 3
forming a polycrystalline silicon charge-trapping layer on the dielectric layer by introducing a precursor gas containing silicon into the chamber
Data Source
AI summary
A method of forming a support substrate having a charge-trapping layer involves introducing a single-crystal silicon base substrate into a deposition chamber and, without removing the base substrate from the chamber and while flushing the chamber with a precursor gas, forming an intrinsic silicon epitaxial layer on the base substrate, then forming a dielectric layer on the base substrate by introducing a reactive gas into the chamber over a first time period, and then forming a polycrystalline silicon charge-trapping layer on the dielectric layer by introducing a precursor gas into the chamber over a second time period. The time for which the dielectric layer is exposed only to the carrier gas, between the first time period and the second time period, is less than 30 seconds and the formation of the charge-trapping layer is performed at a temperature of between 1010° C. and 1200° C.