Charge Trapping Layer P-N Junction Flash Memory
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Solution Overview
Problem
Existing manufacturing processes for flash memories do not fully meet the increasing reliability requirements, particularly in terms of data storage and erase operations, leading to inefficiencies and higher erase operation voltages.
Innovation Solution
A semiconductor device structure is developed with a charge trapping layer comprising N-type and P-type oxynitride semiconductor materials, forming a P-N junction that enhances internal built-in electric fields to improve data storage reliability and reduce erase operation voltage by preventing electron flow to the gate electrode, thereby simplifying the peripheral charge pump circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing manufacturing processes are used for flash memories, then the manufacturing process is relatively simple, but the data storage reliability does not meet increasing reliability requirements
Solution Approach 1:
The charge trapping layer is formed as a composite structure comprising multiple semiconductor layers with different conductivity types (first conductivity type and second conductivity type). This composite structure creates internal built-in electric fields at the interfaces between layers of opposite conductivity, thereby enhancing charge trapping capability and data storage reliability without requiring excessive structural complexity
Solution Approach 2:
Different regions of the charge trapping layer are assigned different conductivity types to create localized functional zones. The first semiconductor layer with first conductivity type and the second semiconductor layer with second conductivity type are positioned at specific locations to generate internal electric fields precisely where needed for improved charge confinement and data storage
2Use of energy by moving object
If existing flash memory structures are used, then the device structure is simpler, but the erase operation voltage is higher
Solution Approach 1:
The invention changes the electrical parameters of the charge trapping layer by incorporating semiconductor layers with different conductivity types. This creates internal built-in electric fields that modify the voltage distribution across the gate stack, thereby reducing the erase operation voltage required while maintaining effective charge erasure functionality
Solution Approach 2:
The gate stack incorporates a composite charge trapping layer with multiple semiconductor layers of different conductivity types. This composite structure generates internal electric fields that assist in charge removal during erase operations, reducing the external voltage required from the charge pump circuitry
3Ease of operation
If higher erase operation voltages are used, then data can be erased, but the peripheral charge pump circuitry becomes more complex
Solution Approach 1:
The charge trapping layer structure generates internal built-in electric fields that actively assist in the charge trapping and erasure processes. This self-generated electric field reduces the burden on external charge pump circuitry, allowing for simpler peripheral circuits while maintaining effective erase operation capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device structure achieves improved data storage reliability and reduced erase operation voltage, enhancing the overall efficiency and reliability of flash memory devices while simplifying the manufacturing process.
Implementation Method 1
A semiconductor device structure is developed with a charge trapping layer comprising N-type and P-type oxynitride semiconductor materials, forming a P-N junction that enhances internal built-in electric fields
Implementation Method 2
forming a P-N junction that enhances internal built-in electric fields to improve data storage reliability and reduce erase operation voltage by preventing electron flow to the gate electrode
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The gate stack includes a first insulating layer, a charge trapping structure, a second insulating layer, and a gate electrode. The first insulating layer separates the semiconductor substrate from the charge trapping structure. The charge trapping structure is between the first insulating layer and the second insulating layer. The gate electrode is over the second insulating layer. The charge trapping structure includes a first layer and a second layer. The first layer includes zinc oxide, tin dioxide, titanium oxide, zinc tin oxide, indium oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxynitride, tin oxynitride, titanium oxynitride, zinc tin oxynitride, indium oxynitride, indium zinc oxynitride, or indium gallium zinc oxynitride. The second layer includes nickel oxide, tin oxide, copper oxide, nickel oxynitride, tin oxynitride, or copper oxynitride. The semiconductor device structure includes a first doped region and a second doped region in the semiconductor substrate and on two opposite sides of the gate stack.