Charge Trapping Layer for High Resistivity SOI Substrates
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Solution Overview
Problem
High resistivity semiconductor-on-insulator wafers for RF devices face issues with parasitic power losses due to charge inversion or accumulation layers at the buried oxide/handle interface, which reduce the effective resistivity and cause device nonlinearity, especially at high frequencies.
Innovation Solution
A multilayer structure is created with a high resistivity single crystal semiconductor handle substrate having a roughened front surface and a charge trapping layer of polycrystalline silicon, which is bonded to a dielectric layer and a single crystal semiconductor device layer, using ion implantation and thermal annealing to form an agglomeration layer and enhance surface roughness for effective charge trapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high resistivity semiconductor-on-insulator wafer is used for RF devices, then the effective resistivity is improved, but parasitic power losses occur due to charge inversion or accumulation layers at the buried oxide/handle interface
Solution Approach 1:
A charge trapping layer comprising polycrystalline silicon is introduced as an intermediary layer between the handle substrate and the buried oxide layer. This intermediate layer captures and traps charges that would otherwise form inversion or accumulation layers at the interface, thereby preventing parasitic power losses while maintaining high effective resistivity for RF device operation.
Solution Approach 2:
The invention converts the harmful effect of charge accumulation at the interface into a beneficial effect by deliberately creating a charge trapping layer that captures these charges. The polycrystalline silicon layer, with its high density of trap states, transforms the problematic charge inversion/accumulation phenomenon into a useful charge trapping mechanism that protects the RF device performance.
2Reliability
If a charge trapping layer is formed on a smooth surface, then charge trapping capability is reduced, but surface preparation becomes simpler
Solution Approach 1:
The invention applies local quality by creating a roughened surface region specifically at the interface between the handle substrate and the charge trapping layer. This localized surface roughness, achieved through controlled etching or mechanical means, enhances the trapping capability in the critical interfacial region without requiring the entire surface to be roughened, thus balancing performance with manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively traps charges and reduces parasitic conduction, maintaining high resistivity even in the near-surface region, thereby improving RF device performance by minimizing transmission line losses and harmonic distortions.
Implementation Method 1
The approach effectively traps charges and reduces parasitic conduction
Implementation Method 2
using ion implantation and thermal annealing to form an agglomeration layer
Implementation Method 3
using ion implantation and thermal annealing to form an agglomeration layer
Data Source
AI summary
A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.