Charge Trapping Layer for SOI Wafer Thermal Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for producing semiconductor-on-insulator wafers with charge trapping layers are prone to thermal instability, leading to reduced charge trapping efficiency due to defect annealing during high-temperature thermal processes, which affects the performance of RF devices.
Innovation Solution
A method involving the deposition of a multilayer charge trapping layer comprising semiconductor materials like silicon, SiGe, or SiC on a high resistivity single crystal handle substrate, followed by oxidation to form a semiconductor oxide layer, which enhances thermal stability and defectivity, thereby improving charge trapping efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a charge trapping layer is formed using conventional methods, then charge trapping efficiency is initially improved, but thermal stability deteriorates during high-temperature thermal processes due to defect annealing
Solution Approach 1:
The patent applies preliminary action by forming the charge trapping layer with specific defect characteristics before the high-temperature thermal processes occur. The layer is intentionally designed with controlled defect density and composition that will maintain charge trapping functionality even after subsequent thermal annealing, preventing the deterioration that would normally occur
Solution Approach 2:
The patent changes material parameters by using specific semiconductor materials (such as silicon germanium or silicon carbide) with tailored compositions and defect densities. By adjusting these material parameters, the charge trapping layer maintains its effectiveness through high-temperature processing without suffering from conventional defect annealing issues
2Reliability
If high resistivity is used in the handle substrate to prevent conductivity issues, then RF device performance is improved, but charge accumulation at interfaces increases leading to non-linear behavior
Solution Approach 1:
The patent introduces an intermediary charge trapping layer between the high resistivity handle substrate and the buried oxide layer. This intermediary layer acts as a buffer that traps charges before they can accumulate at the interface, thereby preventing the non-linear behavior while maintaining the benefits of high resistivity substrate for RF device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in thermally stable charge trapping layers that maintain effectiveness throughout semiconductor-on-insulator fabrication and device manufacturing, enhancing the performance of RF devices by preventing conductivity issues and non-linear behavior.
Implementation Method 1
the deposited semiconductor material layer is oxidized to form a semiconductor oxide layer
Implementation Method 2
A charge trapping layer is formed in a handle substrate at a region near an interface with a buried oxide layer
Data Source
Figure 1~2
Figure 3
AI summary
A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.