Charge Trapping Memory Cell With Assist Site For High Speed Programming
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Solution Overview
Problem
Conventional charge trapping memory technologies face inefficiencies in programming and erasing due to charge accumulation and varying erasing speeds, leading to poor endurance and a narrowed threshold voltage window, especially as technology scales down.
Innovation Solution
The implementation of a turn-on-mode assist-charge (TOM-AC) method, where a charge trapping memory cell has a first assist charge site and a data site, both initially erased to a negative threshold voltage, with the assist site programmed to a high voltage threshold using channel hot electrons, creating a voltage differential to enhance programming and erasing speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hot hole injection is used to erase the cell, then the cell can be erased, but oxide damage occurs leading to charge loss and increased erasing time
Solution Approach 1:
The charge trapping layer is divided into multiple discrete charge trapping sites distributed across the layer. This segmentation allows different regions to experience different voltage conditions during programming and erasing, enabling selective charge trapping and releasing without causing uniform oxide damage throughout the entire structure.
Solution Approach 2:
Different regions of the charge trapping layer are given different properties through the discrete site distribution. Sites closer to the tunneling barrier experience different charge accumulation characteristics compared to sites farther away, creating local variations in threshold voltage and charge retention that improve overall reliability while reducing global oxide damage.
2Ease of manufacture
If direct tunneling is used for charge injection, then programming is simple, but the threshold voltage window becomes narrow and endurance deteriorates
Solution Approach 1:
The invention introduces dynamic voltage modulation during the programming process. By varying the gate voltage over time in a controlled manner, the system can selectively activate different charge trapping sites based on their individual threshold characteristics, enabling precise control of charge distribution without requiring overly simple or complex static voltage schemes.
Solution Approach 2:
The invention exploits changes in the electric field distribution parameter during voltage application. As the gate voltage is applied and adjusted, the electric field penetrates differently through the dielectric layers at various locations, creating dynamic charge injection conditions that fill discrete trapping sites in a controlled sequence, thereby expanding the effective threshold voltage window.
3Productivity
If sector erase is performed on N-bit flash memory, then entire sectors can be erased, but erasing speed varies due to process variations resulting in large Vt distribution
Solution Approach 1:
Before performing the sector erase operation, the system first applies a preliminary voltage condition that pre-activates or pre-prepares the charge trapping sites. This preliminary action ensures that all sites within the sector are in a known initial state, allowing the subsequent erase pulse to uniformly affect all sites regardless of their individual variations in threshold voltage or charge accumulation history.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables high-speed programming and erasing operations by limiting program current through the assist site and utilizing band-to-band tunneling induced hot hole injection, resulting in faster data storage and retrieval with improved endurance.
Implementation Method 1
These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases.
Implementation Method 2
The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
Implementation Method 3
Instead of direct tunneling, band-to-band tunneling induced hot hole injection BTBTHH can be used to erase the cell. However, the hot hole injection causes oxide damage
Implementation Method 4
the AC-site of the charge trapping memory cell is programmed to a high voltage threshold level with permanent charges using a channel hot electron technique... Having a high voltage threshold level on the AC-site and a negative voltage threshold level on the data site creates a voltage differential between the AC-site and the data site
Implementation Method 5
both the AC-site and the data site of the charge trapping memory cell are erased to a negative threshold voltage level, −Vt, by FN injection, thereby inducing a hole charge induced channel between the source and drain regions
Data Source
AI summary
A method of high speed programming and erasing of a charge trapping memory using turn-on-mode assist-charge (TOM-AC) operations. The charge trapping memory includes a charge trapping structure overlying a substrate body with source and drain regions. The charge trapping structure includes a charge trapping layer overlying a dielectric layer. The charge trapping layer has an assist charge site (also referred to as AC-site, AC-side, or a first charge trapping site) and a data site (also referred to as data-side or a second charge trapping site). Initially, to place the charge trapping memory cell in a TOM operation, both the AC-site and the data site of the charge trapping memory cell are erased to a negative threshold voltage level, −Vt, by FN injection, thereby inducing a hole charge induced channel between the source and drain regions.