Charge-Trapping Memory Cell Over Erasing Prevention
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Solution Overview
Problem
Charge-trapping memory cells experience over erasing, leading to leakage currents and read errors due to unequal voltage levels across boundary transistors, which is exacerbated in high-cycle memory structures, and existing solutions either waste layout area or prolong programming time.
Innovation Solution
An equalization transistor is used to connect bit lines after erasure, ensuring voltage equality between terminals of boundary transistors, preventing leakage currents and improving over erasing effects without significant layout area impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If boundary transistors are subjected to sequential erasing operations across multiple memory cell blocks, then complete erasing of all memory cells is achieved, but the boundary transistors experience over erasing due to repeated charge removal
Solution Approach 1:
The patent applies preliminary action by introducing an equalization transistor that proactively equalizes voltage levels between bit lines before the over erasing problem occurs. The equalization transistor is activated during the erasing process to maintain balanced voltage conditions across boundary transistors, preventing excessive charge removal while ensuring complete erasing of memory cells.
2Reliability
If boundary transistors are over erased, then complete charge removal is achieved, but leakage currents are generated affecting memory cell operation
Solution Approach 1:
The patent implements feedback by using the equalization transistor to continuously monitor and adjust voltage levels between bit lines during the erasing process. This feedback mechanism ensures that voltage remains balanced, preventing the conditions that lead to leakage currents while maintaining complete charge removal from memory cells.
3Object-affected harmful factors
If an isolating region is added between memory cell blocks to prevent over erasing, then boundary transistor protection is achieved, but layout area is wasted
Solution Approach 1:
The patent uses an equalization transistor as an intermediary component to prevent over erasing of boundary transistors. Instead of physically isolating memory cell blocks with additional regions, the equalization transistor mediates the voltage levels between bit lines, providing protection without consuming extra layout area.
4Object-affected harmful factors
If dummy cells are added between memory cell blocks to prevent over erasing, then boundary transistor protection is achieved, but programming time is prolonged
Solution Approach 1:
The equalization transistor serves as an intermediary that prevents over erasing without requiring dummy cells. By actively managing voltage levels during the erasing process, the equalization transistor eliminates the need for additional dummy cells that would extend programming time, thereby maintaining efficient operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively prevents over erasing and leakage currents, enhancing read accuracy and precision while minimizing layout area usage and programming time.
Implementation Method 1
the first bit line is electrically connected to the second bit line when the charge-trapping memory cell is completely erased to make a voltage level of the first bit line equal a voltage level of the second bit line
Data Source
AI summary
A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.