Charge-Trapping Memory Fabrication With Protected Blocking Layers
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Solution Overview
Problem
The integration of peripheral circuits and memory cell arrays on the same semiconductor substrate is challenging due to the different circuitry structures of IO, core, switching, and storage devices, leading to issues like contamination of blocking layers, erosion of structures, and difficulty in controlling threshold voltage and reducing cell size.
Innovation Solution
A manufacturing method that includes forming isolation structures, well regions, and gate structures on a semiconductor substrate to fabricate IO, core, and switching devices, with a protecting layer to prevent contamination and separate ion implantation processes for precise control of well regions, enabling the formation of nonvolatile charge-trapping memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different circuitry structures are used for IO devices, core devices, switching devices, and storage devices, then device functionality is improved, but manufacturing complexity and integration difficulty increase
Solution Approach 1:
The semiconductor substrate is divided into distinct device regions (memory device area and logic device area) with isolation structures, allowing different circuitry structures to be implemented in different areas while maintaining manageable manufacturing processes
Solution Approach 2:
Different well regions (first-type well regions for P-type devices, second-type well regions for N-type devices) are formed in specific areas to match the local device requirements, enabling each region to have optimized structures for its specific function
2Difficulty of detecting and measuring
If blocking layers are exposed during manufacturing, then device structure visibility is improved, but contamination and erosion of blocking layers occur
Solution Approach 1:
A protecting layer is formed over the blocking layer before subsequent manufacturing steps, preventing contamination and erosion during processing while allowing the device structure to be properly formed
Solution Approach 2:
The protecting layer acts as an intermediary between the blocking layer and the manufacturing environment, shielding the blocking layer from harmful factors while enabling the manufacturing process to proceed
3Productivity
If ion implantation is performed without separation, then manufacturing efficiency is improved, but precise control of well regions and threshold voltage is compromised
Solution Approach 1:
The ion implantation process is segmented into separate first ion implantation and second ion implantation steps, with photoresist layers used to mask specific regions during each step, enabling precise control of well region formation and threshold voltage
Solution Approach 2:
Photoresist layers are formed in advance to define the regions where ion implantation should occur, ensuring that well regions are created with precise spatial control before the actual ion implantation takes place
4Area of moving object
If memory cell size is reduced, then storage density is improved, but structural integrity and manufacturing precision become more difficult to maintain
Solution Approach 1:
Multiple layers (bottom oxide layer, trapping layer, blocking layer, protecting layer) are nested vertically to create the memory structure, allowing compact horizontal dimensions while maintaining sufficient vertical separation for structural integrity
Solution Approach 2:
The memory structure utilizes vertical layering to achieve functionality that would require larger horizontal dimensions, enabling small memory cell footprint while maintaining structural integrity through the stacked architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method allows for the fabrication of nonvolatile charge-trapping memory cells with improved structural integrity and precise control of threshold voltage, facilitating the production of small-sized memory cells with enhanced performance.
Implementation Method 1
forming a first first-type well region under the surface of the semiconductor substrate and in the memory device area
Data Source
AI summary
A manufacturing method for a nonvolatile charge-trapping memory apparatus is provided. During the manufacturing process of the nonvolatile memory apparatus, a blocking layer of a storage device is effectively protected. Consequently, the blocking layer is not contaminated or thinned. Moreover, since the well regions of the logic device area and the memory device area are not simultaneously fabricated, it is feasible to fabricate small-sized nonvolatile memory cell in the memory device area and precisely control the threshold voltage of the charge trapping transistor.