Charge Trapping Memory Device Uniform Field Distribution
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Solution Overview
Problem
As feature sizes in flash memory devices shrink below 45 nm, floating gate memory cells degrade due to interference and SONOS-type memory cells suffer from non-uniform charge injection, leading to performance degradation with uneven threshold voltage along the channel width.
Innovation Solution
Incorporating a conductive layer between the tunnel dielectric and dielectric charge trapping structure to distribute the electric field uniformly across the channel, maintaining a constant threshold voltage despite non-uniform charge concentration, using a tunneling barrier dielectric structure with an effective oxide thickness greater than 3 nanometers and a conductive layer covering the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric charge trapping structure is used to eliminate coupling ratio engineering, then the device can be planar with less interference between adjacent cells, but non-uniform charge injection occurs due to fringing fields resulting in uneven threshold voltage along the channel width
Solution Approach 1:
A conductive layer is introduced as an intermediary between the charge trapping structure and the channel. This conductive layer acts as a field-distributing medium that receives non-uniform electric fields from the charge trapping structure and redistributes them uniformly across the channel width, thereby decoupling the charge injection process from the threshold voltage distribution outcome
Solution Approach 2:
The invention changes the electrical parameters of the structure by introducing a conductive layer with specific conductivity characteristics. This layer modifies the electric field distribution parameters, transforming the non-uniform field caused by fringing effects into a uniform field that produces consistent threshold voltage across the channel width
2Productivity
If feature size is reduced to increase storage density, then more memory cells can be packed, but floating gate memory cells degrade due to interference between neighboring floating gates
Solution Approach 1:
The conductive layer serves as a field-distributing intermediary that isolates each memory cell's electric field from neighboring cells. By uniformly distributing the electric field within each cell, it prevents field leakage and interference to adjacent cells, enabling higher storage density without performance degradation
Solution Approach 2:
The invention applies local quality enhancement by introducing a conductive layer specifically positioned between the charge trapping structure and channel. This localized modification creates uniform electric field distribution precisely where needed at each memory cell location, preventing interference while maintaining high density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures a more consistent threshold voltage along the channel width, reducing performance degradation and improving the reliability of flash memory devices at smaller feature sizes by evenly distributing the electric field and counteracting uneven charge distribution.
Implementation Method 1
The conductive layer acts to counteract uneven charge distribution in the charge trapping layer by establishing an equipotential surface over the channel and over the tunnel dielectric, distributing the electric field affected by the charge trapped in the charge trapping layer
Implementation Method 2
a tunneling barrier dielectric structure disposed above the channel region with a thickness and dielectric characteristics sufficient to suppress direct tunneling to the charge trapping layer from the substrate
Data Source
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AI summary
A memory cell (100) comprising: a semiconductor substrate (104) with a surface with a source region (102) and a drain region (103) disposed below the surface of the substrate and separated by a channel region 'L'; a tunnelling barrier dielectric structure (105) with an effective oxide thickness of greater than 3 nanometers disposed above the channel region; a conductive layer (101) disposed above the tunnelling barrier dielectric structure (105) and above the channel region 'L'; a charge trapping structure (106) disposed above the conductive layer (101) and above the channel region 'L'; a top dielectric structure (107) disposed above the charge trapping structure (106) and above the channel region 'L'; and a top conductive layer (108) disposed above the top dielectric structure (107) and above the channel region 'L' are described along with devices thereof and methods for manufacturing.