Charge-Trapping Carrier Substrate Deposition Without Low-Temp Seed Layer
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Solution Overview
Problem
Existing methods for preparing support substrates with charge trapping layers are time-consuming and require a seed portion formation at low temperatures, limiting the production rate without compromising quality.
Innovation Solution
A method involving the formation of an intrinsic silicon epitaxial layer followed by a dielectric layer, with a controlled transition period of less than 30 seconds, allows for the direct growth of a polycrystalline silicon charge trapping layer at temperatures between 1010°C and 1200°C, enhancing the growth rate without compromising quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a seed layer is formed at low temperature (below 1010°C) to ensure quality, then the charge trapping layer can be formed without excessive substrate deformation, but the deposition rate is particularly slow (0.3 microns per minute at 900°C)
Solution Approach 1:
The patent changes the temperature parameter from low (below 1010°C) to high (1010°C to 1200°C) to increase deposition rate while maintaining quality through controlled atmosphere and timing
Solution Approach 2:
The patent performs preliminary oxidation to create a dielectric layer surface that enables direct high-temperature deposition without requiring a separate seed layer formation step
2Productivity
If the deposition temperature is increased to improve the deposition rate, then the production time is reduced, but the substrate may undergo excessive deformation that prevents assembly by molecular adhesion
Solution Approach 1:
The patent optimizes multiple parameters simultaneously: temperature (1010-1200°C), atmosphere control (evacuating oxidizing gas before precursor introduction), and timing (controlled transition period) to achieve high deposition rate while limiting substrate deformation
Solution Approach 2:
The patent maintains continuous process control from oxidation through deposition without removing the substrate from the chamber, ensuring consistent conditions that prevent excessive deformation while maintaining high productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly increases the production rate of support substrates by allowing high-quality charge trapping layers to be formed quickly, with improved radiofrequency performance and reduced deformation.
Implementation Method 1
a silicon-containing precursor gas is introduced into the chamber to deposit, by CVD, a polycrystalline silicon charge trapping layer directly on the dielectric layer
Implementation Method 2
a reactive gas is introduced into the chamber to form a dielectric layer on an exposed face of the intrinsic silicon epitaxial layer
Implementation Method 3
the step of forming the charge trapping layer is carried out at a temperature strictly between 1010°C and 1200°C
Data Source
Figure 1~2
Figure 3
AI summary
The invention relates to a method for preparing a carrier substrate (1) provided with a charge-trapping layer. The method comprises placing a base substrate (2) made of monocrystalline silicon exhibiting a resistivity lower than or equal to 500 ohm.cm in a chamber of a deposition apparatus and, without removing the base substrate (2) from the chamber and while sweeping the chamber with a precursor gas, carrying out the following steps: - forming an epitaxial layer of intrinsic silicon (5) on the base substrate (2); - forming a dielectric layer (3) on the base substrate (2) while adding a reactive gas to the chamber for a first period of time; - forming a charge-trapping layer (4) made of polycrystalline silicon directly on the dielectric layer (3) while adding a precursor gas containing silicon to the chamber for a second period of time after the first. The duration for which the dielectric layer (3) is exposed only to the carrier gas, between the first period of time and the second period of time, is shorter than 30 seconds and the formation of the charge-trapping layer (4) is carried out at a temperature of between 1010°C and 1200°C.