Charge-Trapping Transistor Synapse for Neuromorphic Computing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current analog memory devices are not compact, reliable, or continuously tunable enough for large-scale neuromorphic computing applications, particularly due to the lack of effective plastic synapses, which are essential for self-adaptive systems.
Innovation Solution
The use of charge-trapping transistors (CTTs) with high-k gate dielectrics, where short pulses modify the trapped charge states, enabling efficient and stable plastic synapse behavior, and integration with CMOS circuits for adaptive learning and neuromorphic systems, utilizing existing materials and processes for scalability and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If digital SRAM is used to implement synapses, then reliability is improved, but area occupancy increases significantly
Solution Approach 1:
The patent uses charge-trapping transistors to create analog synapse devices that replicate biological synapse behavior without requiring the complex digital circuitry of SRAM. By trapping charges in the high-k dielectric layer, the system creates a compact analog representation of synaptic weights, achieving SRAM-level reliability with much smaller area footprint.
Solution Approach 2:
The invention changes the operational parameter from digital (discrete states) to analog (continuous threshold voltage modulation). By controlling the amount of trapped charge through pulse width and amplitude, the system achieves continuous tunability of synaptic weights, enabling compact implementation while maintaining reliability through physical charge storage.
2Area of stationary object
If analog memory devices are made compact, then integration density is improved, but uniformity and reliability deteriorate
Solution Approach 1:
The patent employs standard CMOS fabrication processes to create homogeneous charge-trapping transistor structures across the chip. The use of uniform high-k dielectric materials and consistent pulse programming schemes ensures that devices of the same type exhibit similar charge-trapping characteristics, achieving good uniformity despite compact dimensions.
Solution Approach 2:
The system incorporates readout circuits that measure the threshold voltage of each synapse device and use this information to adjust subsequent programming pulses. This feedback mechanism compensates for device-to-device variations, ensuring reliable and uniform synaptic weight storage across compact device arrays.
3Adaptability or versatility
If exotic materials are used for analog memory, then analog continuity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent achieves analog continuity by modulating the threshold voltage of standard CMOS transistors through controlled charge trapping. By varying the width and amplitude of programming pulses, the system creates a continuous range of synaptic weights using conventional semiconductor materials and processes, avoiding the need for exotic analog memory materials.
Solution Approach 2:
The invention uses standard, readily available high-k dielectric materials that are already integrated into modern CMOS processes. These materials can be deposited using existing fabrication techniques, eliminating the need for complex material deposition and processing required by exotic analog memory materials, thereby simplifying manufacturing.
4Device complexity
If charge-trapping transistors are used for plastic synapses, then device complexity is reduced, but achieving stable charge-trapping requires precise control
Solution Approach 1:
The patent uses periodic pulse sequences to program and read synapse weights. By applying a series of identical programming pulses with controlled width and amplitude, the system achieves stable charge trapping through repeated action, compensating for any single-pulse variability and simplifying the control requirements.
Solution Approach 2:
The system maintains continuous control over synaptic weights through persistent charge trapping in the dielectric layer. Once charged, the trapped electrons remain stored, maintaining the synaptic weight without requiring continuous power or control signals, thereby reducing operational complexity while maintaining precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
CTTs provide small, uniform, energy-efficient, and cost-effective plastic synapses for neuromorphic applications like pattern recognition and adaptive learning, exhibiting spike timing-dependent plasticity and weight-dependent plasticity, facilitating the development of large-scale neuromorphic systems.
Implementation Method 1
charge-trapping phenomenon in high-k gate dielectrics of advanced-node FETs
Implementation Method 2
Charge-trapping in high-k gate dielectrics can be rendered more efficient and more stable in the presence of an appropriate drain bias
Data Source
AI summary
A fine-grained analog memory device includes: 1) a charge-trapping transistor including a gate and a high-k gate dielectric; and 2) a pulse generator connected to the gate and configured to apply a positive or negative pulse to the gate to change an amount of charges trapped in the high-k gate dielectric.