Charge Trapping Transistors for Leakage Control
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Solution Overview
Problem
Conventional semiconductor devices with volatile memory cells experience sub-threshold leakage current and gate-induced drain leakage, leading to high refresh rates and failed memory cells due to inadequate charge retention and drive current issues.
Innovation Solution
The use of a charge trapping material in transistors, such as silicon nitride, is implemented to control charge trapping properties, reducing gate-induced drain leakage and enhancing drive current by adjusting the extent of charge trapping in individual memory cells, thereby improving the yield and performance of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate electrode overlaps sufficiently with the source and drain regions to increase drive current, then the drive current is improved, but gate-induced drain leakage increases
Solution Approach 1:
The patent applies local quality by creating different overlap configurations for different transistors within the same semiconductor device. Specifically, first transistors have a first overlap extent between gate electrode and source/drain regions, while second transistors have a second overlap extent that is less than the first. This localized variation allows each transistor type to be optimized for its specific function - some for high drive current, others for low leakage - without affecting the entire device uniformly.
2Power
If the extent of overlap of the gate electrode with the source and drain regions is increased to improve drive current, then the drive current is improved, but the refresh rate increases due to higher leakage
Solution Approach 1:
The patent implements local quality by differentiating overlap extents across different transistor groups. First transistors with greater overlap provide high drive current for write operations, while second transistors with reduced overlap minimize leakage for read operations and charge retention. This spatial differentiation of structural properties allows simultaneous optimization of both drive current and refresh rate characteristics in different parts of the memory device.
3Device complexity
If conventional transistors are used without charge trapping material, then the device complexity is low, but the number of failed memory cells increases due to inadequate charge retention
Solution Approach 1:
The patent applies preliminary action by pre-configuring transistors with charge trapping materials and varied overlap extents during manufacturing, before the memory device is put into service. This preliminary structural configuration ensures that transistors are pre-optimized for their specific roles (high drive current vs. low leakage) without requiring runtime adjustment or calibration, thereby improving yield and reliability from the outset.
Solution Approach 2:
The patent utilizes parameter changes by modifying the overlap extent parameter and material composition parameter of transistors. Specifically, the overlap extent is varied between first and second transistors, and charge trapping materials are introduced to alter the electrical characteristics. These parameter modifications enable precise control over drive current and leakage characteristics, improving device performance and yield.
4Reliability
If the overlap extent is reduced to decrease gate-induced drain leakage, then the refresh rate is improved, but the drive current decreases
Solution Approach 1:
The patent applies local quality by assigning different overlap extents to different transistor groups based on their functional requirements. Second transistors with reduced overlap are positioned where low leakage is critical for maintaining charge retention and refresh rate, while first transistors with greater overlap are used where high drive current is needed for write operations. This localized optimization ensures both parameters are satisfied in their respective contexts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a reduced number of failed memory cells, improved refresh rates, and increased drive current, leading to enhanced data write times and overall semiconductor device performance.
Implementation Method 1
a charge trapping material in contact with the oxide material and the dielectric material... The charge trapping material may include, for example, silicon nitride, silicon oxynitride, tantalum oxide, titanium oxide, hafnium silicate, hafnium aluminum oxide, or a combination thereof
Data Source
AI summary
A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.