Charge-Trapping Trench Isolation for Leakage Control

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Solution Overview

Problem

In modern semiconductor technology, improper electrical isolation of devices can cause current leakage, leading to power loss, reduced functionality, and issues such as latch-up, noise margin degradation, and cross-talk, particularly in highly integrated semiconductor chips.

Innovation Solution

A method for forming an isolation structure that replaces the need for a doped region by using a charge-trapping layer, eliminating the requirement for ion implantation and photolithography, and includes a sequence of forming trenches, insulating layers, and charge-trapping layers to enhance electrical isolation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ion implantation and photolithography are used to form doped regions for electrical isolation, then electrical isolation between devices is improved, but device complexity and manufacturing process complexity increase

Engineering Contradiction:
Improveelectrical isolationVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the doped region formation steps (ion implantation and photolithography) from the isolation structure fabrication process. Instead of forming doped regions, the invention uses a simplified approach with trenches filled with dielectric material and charge-trapping layers, removing complex manufacturing steps while maintaining electrical isolation functionality

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the fundamental parameters of the isolation structure by replacing doped semiconductor regions with undoped regions combined with charge-trapping layers. This parameter change eliminates the need for ion implantation processes while achieving equivalent or superior electrical isolation through different physical mechanisms

Inventive Principle:
Principle #35Parameter changes

2Reliability

If ion implantation is used to form doped regions, then electrical isolation is improved, but substrate damage and defects increase

Engineering Contradiction:
Improveelectrical isolationVSAvoidsubstrate damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent converts the harmful effect of ion implantation (substrate damage) into a beneficial approach by completely eliminating ion implantation from the process. Instead of trying to mitigate damage, the invention uses a different mechanism (charge-trapping layers in undoped regions) that achieves electrical isolation without introducing substrate damage in the first place

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent introduces charge-trapping layers as intermediary elements between the dielectric material and the semiconductor substrate. These charge-trapping layers provide the necessary electrical isolation and field control functions without requiring direct doping of the substrate, thereby avoiding ion implantation damage

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces electron leakage and substrate damage, improving device performance and functionality by minimizing defects and leakage currents, especially in image sensor arrays.

Implementation Method 1

A charge-trapping layer is formed on the first insulating layer... effectively reduces electron leakage

Methodology Applied
Scientific EffectCharge trapping: Absorption (physical)

Data Source

PatentUS12568700B2Method for forming isolation structure and semiconductor structure
Publication Date: 2026.03.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12568700B2 patent drawing
  • US12568700B2 patent drawing
  • US12568700B2 patent drawing

AI summary

A method for forming an isolation structure includes following operations. A trench is formed in a semiconductor substrate. A first insulating layer covering a bottom and sidewalls of the trench is formed. A charge-trapping layer is formed on the first insulating layer. The trench is filled with a second insulating layer. The charge-trapping layer include a material different from those of the first insulating layer and the second insulating layer.