Charged Dipole Layers for Vertical Gate-All-Around FET Resistance
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Solution Overview
Problem
Vertical field-effect transistor (VFET) devices face performance degradation due to high resistance in undoped regions at the tops of the fins, which are inevitable due to thermal constraints after high-κ metal gate formation, especially when channel length is scaled for fins of a given height.
Innovation Solution
Forming dipoles in the undoped regions at the tops of the VFETs by depositing charged layers that induce opposite charges, reducing resistance and enhancing current flow, with positively charged layers used for n-channel FETs and negatively charged layers for p-channel FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel length is scaled down for fins of a given height, then device integration density is improved, but resistance in undoped regions increases due to longer undoped region length
Solution Approach 1:
The patent applies local quality by forming dipoles specifically in the undoped regions at the tops of the fins, creating localized charge structures that reduce resistance only where needed. This targeted approach allows channel length scaling for higher integration density while compensating for the increased resistance in the undoped regions through localized dipole formation, thus resolving the contradiction between integration density and device performance.
2Reliability
If dipoles are formed in undoped regions, then resistance is reduced and current flow is enhanced, but device complexity increases
Solution Approach 1:
The patent uses dipoles as intermediary structures formed in the undoped regions. These dipoles act as mediators that reduce resistance and enhance current flow without requiring fundamental changes to the high-κ metal gate architecture. By introducing this intermediate dipole formation step, the patent improves device performance while adding only moderate complexity to the fabrication process, resolving the contradiction between performance improvement and fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of dipoles in the undoped regions reduces resistance and improves VFET performance by facilitating efficient electron or hole flow through these regions, thereby enhancing device performance.
Implementation Method 1
depositing a charged layer over the at least one fin in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the at least one fin forming a dipole
Data Source
AI summary
Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques.