Charged Particle Lithography for Unique Semiconductor Chip Identification
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Solution Overview
Problem
The semiconductor industry faces challenges in creating unique semiconductor chips with unique circuits, as mask-based photolithography is expensive and introduces security risks, while existing maskless lithography methods require high processing power and memory for each unique chip design.
Innovation Solution
The use of charged particle multi-beamlet lithography allows for the creation of unique semiconductor chips with non-common structures and circuits that can store or generate predetermined values, such as serial numbers or cryptographic keys, by forming unique patterns directly on the chip during manufacturing, enabling high information density and secure authentication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If mask-based photolithography is used to create unique chips, then manufacturing precision and reliability are improved, but device complexity and cost increase due to expensive masks and security risks
Solution Approach 1:
The patent extracts the unique identification function from the main chip circuit and implements it separately using charged particle beam lithography. This allows the unique features to be added after the main chip fabrication, avoiding the need for complex masks for the entire chip while maintaining manufacturing precision for the unique identifiers.
Solution Approach 2:
The patent performs preliminary fabrication of common chip structures using standard photolithography, then adds unique features in a subsequent step using charged particle beam lithography. This preliminary action approach separates the manufacturing process into common and unique parts, reducing overall complexity.
2Device complexity
If maskless lithography is used to create unique chips, then device complexity and cost are reduced, but productivity decreases due to high processing power and memory requirements
Solution Approach 1:
The patent segments the lithography process into two parts: common chip structures fabricated using efficient mask-based photolithography for high throughput, and unique identification features added using maskless charged particle beam lithography. This segmentation allows each method to be used where it is most effective.
Solution Approach 2:
The patent applies different lithography methods to different parts of the chip: standard photolithography for the common circuit structures and charged particle beam lithography for the unique identification features. This local quality approach optimizes both productivity and uniqueness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of secure, unique semiconductor chips with high information storage density, reducing the need for expensive masks and minimizing processing power, while maintaining control over the unique design data, thus enhancing security and efficiency in chip manufacturing.
Implementation Method 1
The pattern data that is input to the exposure system, representing the unique electronic devices or chips to be created, may be made unique by using a different design layout data input file, e.g. a GDSII or OASIS input file, for each unique electronic device to be created.
Data Source
Figure 1
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Figure 4A
AI summary
An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non-common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a second portion of the non-common structures is adapted to store or generate a first predetermined value which uniquely identifies the first non-common circuit, wherein the first predetermined value is readable from outside the semiconductor chip by automated reading means.