Charged Punch-Through Stopper Layer for FinFET Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices, particularly FinFETs, the formation of an abrupt punch-through stopper (PTS) layer with a high dopant concentration in the sub-fin portion while maintaining zero dopant concentration in the fin is challenging, leading to leakage issues due to punch-through effects.
Innovation Solution
A charged punch-through stopper layer with net negative or positive charges is formed on the side walls of the fin structure beneath the fin, introducing electrons or holes into the sub-fin to create a potential barrier, suppressing leakage current between source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If ion implantation and thermal diffusion are used to form a PTS layer, then dopant concentration can be increased in the sub-fin portion, but dopants may be introduced into the fin causing leakage
Solution Approach 1:
The patent applies local quality by forming the PTS layer only in the sub-fin portion beneath the fin, with a sharp spatial boundary. The PTS layer is confined to regions where x² + y² ≤ (Rfin + ΔR)² and z ≤ Hfin, ensuring high dopant concentration is localized exactly where needed to suppress punch-through, while the fin region remains dopant-free to prevent leakage.
Solution Approach 2:
The patent segments the fin structure into two distinct regions: the fin portion (z > Hfin) and the sub-fin portion (z ≤ Hfin). This segmentation allows different dopant concentrations to be applied to each region independently, with the PTS layer formed only in the sub-fin portion to suppress punch-through without affecting the fin's electrical properties.
2Reliability
If a PTS layer is formed to suppress punch-through, then leakage current is reduced, but achieving an abrupt dopant distribution is difficult
Solution Approach 1:
The patent applies preliminary action by pre-defining the sharp boundary of the PTS layer formation region using the mathematical condition x² + y² ≤ (Rfin + ΔR)² before dopant introduction. This pre-established geometric boundary ensures that when ions are implanted or diffusion occurs, the dopant distribution automatically achieves the desired abrupt profile at the PTS layer edge, eliminating the need for additional masking or patterning steps.
Solution Approach 2:
The patent introduces a geometric boundary condition (x² + y² ≤ (Rfin + ΔR)²) as an intermediary to mediate between the dopant source and the fin structure. This mathematical boundary acts as a virtual mask that guides dopant placement, ensuring sharp spatial separation between the PTS layer and fin region without requiring physical masking layers that would complicate the manufacturing process.
3Area of moving object
If the fin structure is scaled down to reduce device size, then device density increases, but short channel effects and punch-through become more significant
Solution Approach 1:
The patent introduces a charged PTS layer as an intermediary structure between the source/drain regions and the channel. This charged layer creates an electric field that compensates for the short channel effects, effectively extending the depletion region and preventing punch-through leakage even in scaled-down devices with reduced channel length.
Solution Approach 2:
The patent changes the electrical parameters of the sub-fin portion by introducing a charged PTS layer with specific charge density. This modifies the electric field distribution and potential profile in the short channel region, creating a virtual drain extension that suppresses punch-through effects and improves device reliability despite reduced dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The charged PTS layer effectively reduces punch-through leakage, maintaining a distance between the well and fin surfaces, minimizing dopant influence and random dopant fluctuation, and stabilizing the threshold voltage.
Implementation Method 1
a punch-through stopper (PTS) layer may be formed (beneath the fin) by ion implantation and/or thermal diffusion
Implementation Method 2
a punch-through stopper (PTS) layer may be formed (beneath the fin) by ion implantation and/or thermal diffusion
Data Source
AI summary
Provided are a semiconductor device having a charged punch-through stopper (PTS) layer to reduce punch-through and a method of manufacturing the same. In an embodiment, the semiconductor device may include a fin structure formed on a substrate; an isolation layer formed on the substrate, wherein a portion of the fin structure above the isolation layer acts as a fin of the semiconductor device; a charged PTS layer formed on side walls of a portion of the fin structure beneath the fin; and a gate stack formed on the isolation layer and intersecting the fin. The semiconductor device may be an n-type device or a p-type device. For the n-type device, the PTS layer may have net negative charges, and for the p-type device, the PTS layer may have net positive charges.