Check Node Compression for Faster Memory Integrity Checks
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Solution Overview
Problem
Existing memory systems face inefficiencies in register usage and memory access performance due to the generation and storage of check node data during integrity checks, particularly in solid-state drives, which is costly and hinders optimal performance.
Innovation Solution
Compressing check node data by identifying significant bits and determining a set of data bits that uniquely represent the value combinations, reducing the number of bits required for storage while maintaining data integrity, and adaptively reconfiguring memory space to store different numbers of check nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If check node data is stored in registers during integrity check process, then data validation can be performed, but register usage increases and memory access performance deteriorates
Solution Approach 1:
The patent extracts only the most significant bits (MSBs) from check node data for storage in registers, removing less critical information. This selective extraction reduces the amount of data stored while maintaining the essential error detection capability, directly resolving the contradiction between validation reliability and register usage complexity
Solution Approach 2:
The patent changes the parameter of data representation by encoding check node data using a variable number of bits based on the actual value combinations present. Instead of storing fixed-width data, the system dynamically adjusts the number of bits required, reducing register usage while preserving the necessary validation information
2Reliability
If check node data is stored in registers, then integrity checking can proceed, but memory access performance decreases
Solution Approach 1:
By extracting and storing only the essential MSBs of check node data in registers, the patent reduces memory access overhead. The reduced data volume allows for faster register operations and improved memory access performance while maintaining the core integrity checking function
Solution Approach 2:
The patent segments check node data into most significant bits and less significant bits, storing only the critical MSBs in registers. This segmentation allows the system to perform integrity checks with reduced data, improving memory access performance while preserving validation capability
3Ease of manufacture
If fixed memory space is allocated for check nodes, then storage is simplified, but storage space utilization is inefficient
Solution Approach 1:
The patent implements dynamic memory allocation where the number of bits allocated for storing check node data varies based on the actual value combinations present in the data. This dynamic approach allows the system to efficiently utilize storage space by allocating only the necessary number of bits, improving space utilization while maintaining simplicity through automated bit determination
Data Source
AI summary
This application is directed to compressing check node data for an electronic device. The electronic device identifies a check node corresponding to a subset of codeword symbols in a block of data and determines check node data that indicates a likelihood of the subset of codeword symbols being erroneous. A set of data bits are determined based on a value combination of data items of the check node data to uniquely identify the value combination among a set of selected value combinations according to a predefined relationship. The electronic device stores, in a memory block, the set of data bits representing the data items of the check node data of the check node. Each data item requires more data bits to represent all possible values of the respective data item than data bits of the set of data bits.