Check Node Decoding Architecture for Lower-Complexity Non-Binary LDPC
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Solution Overview
Problem
The high computational complexity and memory requirements of check node processing units in non-binary LDPC code decoders hinder efficient hardware implementations, particularly for longer codes and higher-order Galois fields, leading to increased costs and silicon area usage.
Innovation Solution
A check node processing unit is designed to receive input messages with reliability metrics, store them in a data structure, and apply transformation operations to arrange components based on these metrics, reducing the number of required input messages and computations, using architectures like syndrome-decoding or forward-backward methods to determine output messages efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional check node processing units are used in non-binary LDPC code decoders, then decoding functionality is achieved, but computational complexity and memory requirements increase significantly
Solution Approach 1:
The check node processing unit is segmented into multiple functional blocks including a data structure unit for storing input messages, a transformation operation unit for reorganizing data, and a calculation unit for determining output messages. This segmentation allows each block to perform a specific function with optimized resource usage, reducing overall computational complexity while maintaining decoding performance.
Solution Approach 2:
The patent transforms the computational approach by introducing a new dimension of data organization through transformation operations. Input messages are stored in a data structure and then transformed by reorganizing components based on specific criteria before calculation. This dimensional transformation of the data processing flow reduces the computational burden compared to conventional direct processing methods.
2Reliability
If conventional check node processing units are used in non-binary LDPC code decoders, then decoding functionality is achieved, but hardware costs and silicon area usage increase
Solution Approach 1:
By dividing the check node processing unit into distinct functional blocks (data structure unit, transformation operation unit, calculation unit), the patent enables more efficient hardware utilization. Each block can be implemented with optimized circuitry for its specific function, reducing the total silicon area required compared to a monolithic conventional implementation.
Solution Approach 2:
The patent changes the parameters of data organization and processing flow through transformation operations. By reorganizing message components in the data structure before calculation, the system reduces the number of computational operations required, which directly translates to reduced hardware resources and smaller silicon area while maintaining the same decoding performance.
Data Source
AI summary
Devices and methods for decoding a signal encoded using an error correcting code are provided. For example, a check node processing unit is provided for a decoder to receive at least two input messages and to generate at least one output message, each message comprising a plurality of components. The check node processing unit comprises a data structure configured to store the input messages, the components of the input messages being associated with an integer index. The check node processing unit also comprises a data processing unit configured to apply one or more iterations of a transformation operation to at least a part of the data structure depending on at least some of the components of the input messages associated with a given value of the integer index, which provides a transformed data structure. The check node processing unit further comprises a calculation unit configured to determine at least one output message from the transformed data structure.