Check Node Message Sorting for Low-Latency Non-Binary LDPC Decoding
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Solution Overview
Problem
Existing decoding algorithms for non-binary LDPC codes face high computational complexity and latency issues in check node processing units, particularly due to the complexity of sorting and redundancy elimination operations in elementary check node processors.
Innovation Solution
A low-complexity sorting operation for check node messages is introduced, which reduces latency and complexity by sorting operations that are linear with respect to the number of sorted bubbles, independent of the number of bubbles, and reduces critical paths in decoding signals encoded using non-binary error correcting codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional sorting and redundancy elimination operations are performed in elementary check node processors, then decoding accuracy is maintained, but computational complexity and latency increase significantly
Solution Approach 1:
The patent segments the sorting operation into multiple passes, where each pass sorts only a subset of bubbles rather than performing a complete sort. This segmentation reduces the computational complexity of each individual operation while maintaining the overall decoding accuracy through multiple iterative sorting passes.
Solution Approach 2:
The patent performs preliminary sorting operations on subsets of bubbles before the final redundancy elimination step. By pre-sorting smaller groups of bubbles, the system reduces the complexity of the subsequent full sorting operation while ensuring that the most reliable bubbles are already positioned for efficient selection.
2Productivity
If conventional sorting operations are performed in elementary check node processors, then complete message processing is achieved, but latency increases due to complex sorting requirements
Solution Approach 1:
The sorting operation is divided into multiple segments or passes, where each pass handles a portion of the bubbles. This segmentation allows the system to make progress on sorting without waiting for complete sorting of all bubbles, thereby reducing latency while maintaining processing throughput.
Solution Approach 2:
The patent performs partial sorting operations that sort only enough bubbles to achieve the required decoding accuracy, rather than completely sorting all bubbles. This partial action reduces the time required for sorting while still achieving the necessary processing throughput for reliable decoding.
3Reliability
If sorting operations are performed on all bubbles, then complete redundancy elimination is achieved, but the number of computational operations increases
Solution Approach 1:
The patent extracts and processes only the most reliable bubbles separately from the rest, performing sorting and redundancy elimination on a subset of critical bubbles rather than all bubbles. This extraction approach reduces the number of computational operations while maintaining message reliability by ensuring that the most important bubbles are properly processed.
Solution Approach 2:
The patent applies different processing quality to different bubbles based on their reliability metrics. High-reliability bubbles receive more thorough sorting and processing, while lower-reliability bubbles receive reduced processing. This local quality approach maintains overall message reliability while reducing the total number of computational operations required.
Data Source
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AI summary
A sorting device for determining elementary check node components in an elementary check node processor (3) implemented in a non-binary error correcting code decoder by sorting auxiliary components. The auxiliary components are stored in a plurality of FIFO memories (33-n), each FIFO memory (33-n) being assigned a FIFO number index. Each auxiliary component stored in a given FIFO memory (33-n) comprises an auxiliary symbol, a reliability metrics representing the reliability of the auxiliary symbol, and the FIFO number index assigned to the given FIFO memory (33-n). The sorting device is configured to sort the auxiliary components by a plurality of multiplexers (34-m) arranged sequentially. Each multiplexers (34-m) is configured to initialize a candidate elementary check node component from the components of a FIFO memory corresponding to the auxiliary component which comprise the most reliable auxiliary symbol and to perform one or more iterations of the following steps: - receive an auxiliary component extracted from the FIFO memory (33-n) which is assigned the FIFO number index comprised in the candidate elementary check node component determined at the previous iteration which comprises the most reliable candidate symbol, and - update the candidate elementary check node component determined at the previous iteration by selecting one component among the received auxiliary component, the candidate elementary check node component determined at the previous iteration by the multiplexer (34-m), and the candidate elementary check node component determined at the previous iteration by the subsequent multiplexer (34-(m + 1)). The sorting device is configured to determine, at each of the one or more iterations, an elementary check node component by selecting the candidate elementary check node component which comprises the most reliable candidate symbol.