Check Node Offset Selection for Low-Complexity Non-Binary LDPC Decoding

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Solution Overview

Problem

Current decoding algorithms for non-binary LDPC codes, such as the Extended Min-Sum (EMS) algorithm, require significant computational and storage resources, which are not feasible in devices demanding low complexity and high throughput, especially in real-time applications.

Innovation Solution

The implementation of an elementary check node processing unit that receives messages from variable node processing units, determines auxiliary components with optimal decoding performance values, and transmits an offset value to reduce computational complexity, enabling low-complexity designs for check node processing units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the EMS algorithm is used for decoding non-binary LDPC codes, then decoding performance approaches the Shannon limit, but computational complexity and storage resources increase significantly

Engineering Contradiction:

Improvedecoding performanceVSAvoidcomputational complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent transforms the decoding computations from linear scale to logarithmic scale by introducing offset values. The check node processing unit determines offset values that transform product operations into summation operations, significantly reducing computational complexity while maintaining decoding performance near the Shannon limit

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies different offset values to different components of the check node messages based on their specific characteristics. Each check node processing unit determines offset values tailored to its local requirements, optimizing the balance between computational complexity and decoding accuracy for each specific message component

Inventive Principle:

Principle #3Local quality

2Reliability

If the EMS algorithm is used for decoding non-binary LDPC codes, then decoding performance is optimized, but hardware complexity and latency increase

Engineering Contradiction:

Improvedecoding performanceVSAvoidhardware complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses logarithmic-scale computations with offset values to transform complex product operations into simpler summation operations. This parameter transformation reduces the hardware resources required for implementation while maintaining optimal decoding performance

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent replaces complex multiplication operations with simpler addition operations in the logarithmic domain. This substitution reduces the hardware complexity of the check node processing units by eliminating the need for complex multipliers while preserving decoding accuracy

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If traditional decoding algorithms are used, then decoding accuracy is high, but throughput and latency are unacceptable for real-time applications

Engineering Contradiction:

Improvedecoding accuracyVSAvoidthroughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent transforms computations to logarithmic scale with offset values, enabling faster arithmetic operations. This transformation increases throughput by replacing complex product operations with simpler summation operations, making real-time processing feasible while maintaining high decoding accuracy

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent divides the check node processing into multiple parallel elementary check node processing units, each handling specific message components. This segmentation enables parallel processing, significantly increasing throughput and reducing latency for real-time applications

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11545998B2Offset value determination in a check node processing unit for message-passing decoding of non-binary codes

Publication Date: 2023.01.03 UNIVERSITY OF SOUTHERN BRITTANY

AI summary

Embodiments of the invention provide an elementary check node processing unit (300) implemented in a check node processing unit of a non-binary error correcting code decoder, the elementary check node processing unit (300) being linked to a variable node processing unit (305) and being configured to receive a first message and a second message, each message comprising at least two components. The elementary check node processing unit (300) comprises a calculation unit (301) which determines two or more auxiliary components from the components comprised in the first message and from the components comprised in the second message, an auxiliary component comprising an auxiliary reliability metrics. The calculation unit (301) also determines, in association with each of the two or more auxiliary components, decoding performance values. The elementary check node processing unit (300) also comprises a selection unit (303) which selects, among the two or more auxiliary components, the auxiliary component that is associated with the optimal decoding performance values and determines an offset value from the auxiliary reliability metrics comprised in the selected auxiliary component. The elementary check node processing unit (300) then transmits the offset value and a selected set of auxiliary components among the two or more auxiliary components to the variable node processing unit (305).