Check Node Syndrome Decoding with Reliability Pre-Sorting

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Solution Overview

Problem

Current iterative decoding algorithms for non-binary LDPC codes face high computational complexity and latency issues due to the complexity of check node processing units, particularly in syndrome-based architectures, which are not efficiently adapted for high-order Galois fields and high coding rates.

Innovation Solution

A decoder architecture that includes vector permutation units to presort variable node messages based on reliability metrics, reducing the number of computed syndromes and simplifying elementary check node processors, thereby reducing computational complexity and implementing a low-latency, low-complexity check node processing unit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If syndrome-based architectures are used for check node processing, then decoding accuracy is improved, but computational complexity and hardware costs increase significantly

Engineering Contradiction:
Improvedecoding accuracyVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by presorting variable node messages based on reliability metrics before they enter the syndrome computation stage. This preprocessing step organizes input data in advance, allowing the syndrome-based check node processing to operate more efficiently on already-ordered data, thereby reducing the computational burden during the actual decoding operation while maintaining decoding accuracy

Inventive Principle:
Principle #10Preliminary action

2Reliability

If syndrome-based architectures are used for check node processing, then decoding accuracy is improved, but hardware costs increase

Engineering Contradiction:
Improvedecoding accuracyVSAvoidhardware costs
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

By presorting messages before syndrome computation, the patent reduces the number of computational operations required during the main decoding process. This preliminary organization of data enables simpler hardware implementation of the syndrome-based architecture, as the presorted input reduces the complexity of subsequent processing stages, thereby lowering overall hardware costs while preserving decoding accuracy

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If traditional check node processing is used, then implementation is simpler, but latency increases

Engineering Contradiction:
Improveimplementation complexityVSAvoiddecoding latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent implements preliminary sorting of variable node messages based on reliability metrics before check node processing. This presorting step, while adding a small initial complexity, enables more efficient parallel processing in subsequent stages by organizing data in an optimal order, thereby reducing the overall decoding latency despite the minor overhead of the sorting operation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the check node processing into multiple parallel elementary check node processors that operate simultaneously on different portions of the presorted messages. This segmentation enables pipelined processing where different stages can work concurrently, significantly reducing decoding latency while keeping individual processor implementations relatively simple

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3316486B1Elementary check node-based syndrome decoding with input pre-sorting
Publication Date: 2023.06.14 UNIVERSITY OF SOUTHERN BRITTANY
  • EP3316486B1 patent drawingFigure 1
  • EP3316486B1 patent drawingFigure 2
  • EP3316486B1 patent drawingFigure 3

AI summary

Embodiments of the invention provide a decoder for determining an estimate of an encoded signal, the decoder comprising one or more variable node processing units (23) and one or more check node processing units (25) configured to exchange messages, each message comprising one or more components, a component comprising a symbol and a reliability metric associated with said symbol, wherein the decoder comprises: - at least one vector permutation unit (24) configured to receive a set of at least three variable node messages comprising variable node components from at least one variable node processing unit and to generate permuted messages depending on a plurality of the reliability metrics comprised in said variable node components, the variable node messages being sorted according to an order of the reliability metrics; and - at least one check node processing unit (25-1) configured to: • calculate at two or more elementary check node processors (26) a set of syndromes from said at least three permuted messages, • generate at least one check node message from said set of syndromes, and • send said at least one check node message to a signal estimation unit (29).