Hybrid Check Node Architecture for Low-Complexity NB-LDPC Decoding
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Solution Overview
Problem
Current decoding algorithms for non-binary LDPC codes, such as the Extended Min-Sum (EMS) algorithm, require significant computational and storage resources, leading to high complexity and latency issues, especially in real-time applications and systems demanding high throughput and low latency.
Innovation Solution
A check node processing unit is configured to determine at least two check node messages by using a hybrid architecture that combines syndrome-based and forward-backward architectures, with presorting techniques to permute variable node messages and reduce computational complexity, allowing for dynamic adaptation based on reliability metrics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the EMS algorithm is used for decoding non-binary LDPC codes, then decoding performance is improved, but computational complexity and storage resources increase significantly
Solution Approach 1:
The check node processing is divided into multiple sub-check nodes, each handling a specific subset of computations. This segmentation allows the complex EMS algorithm to be broken down into manageable parts, reducing the computational burden on any single processing unit while maintaining overall decoding performance.
Solution Approach 2:
The patent implements dynamic adaptation of the decoding process based on reliability metrics. The system can adjust its processing strategy dynamically, switching between different computation modes or allocating resources differently based on the current decoding state and reliability requirements, thereby optimizing the trade-off between performance and complexity.
2Reliability
If the EMS algorithm is used for decoding non-binary LDPC codes, then decoding performance is improved, but latency increases
Solution Approach 1:
By segmenting the check node processing into parallel sub-check nodes, the patent enables simultaneous execution of multiple decoding operations. This parallelization reduces the overall latency by eliminating sequential dependencies while preserving the iterative nature of the EMS algorithm.
Solution Approach 2:
The patent performs preliminary computations and preparations before the main decoding iterations begin. By pre-processing certain operations and organizing data structures in advance, the system reduces the computational overhead during actual decoding, thereby lowering latency without compromising performance.
3Reliability
If the EMS algorithm is used for decoding non-binary LDPC codes, then decoding performance is improved, but throughput is reduced
Solution Approach 1:
The patent divides the check node processing unit into multiple sub-check nodes that can operate in parallel, effectively increasing the processing throughput. Each sub-check node handles a portion of the computations, allowing the system to process more data simultaneously while maintaining the performance benefits of the EMS algorithm.
Solution Approach 2:
The sub-check nodes are designed to be multi-functional, capable of performing various decoding operations and adapting to different processing requirements. This universality allows the same hardware structure to handle multiple tasks efficiently, maximizing throughput without sacrificing decoding performance.
Data Source
AI summary
A check node processing unit configured to determine check node messages to decode a signal encoded using NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units configured to determine permuted variable node messages by permuting variable node messages generated by one or more variable node processing units; a syndrome sub-check node configured to determine check node messages from a set of syndromes, the set of syndromes being determined from one or more intermediate messages computed from the permuted variable node messages; a forward-backward sub-check node configured to determine permuted check node messages from the intermediate messages; a switching unit configured to generate check node messages of given index from the check node messages or from the permuted check node messages depending on the giving index.