Checker Processor Segmentation for Error Detection
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Solution Overview
Problem
Existing error detection techniques in data processing systems, such as dual-core lockstep and software redundancy, face challenges in scalability, power consumption, and effectiveness, especially for complex processors, and fail to adequately address the increasing occurrence of transient faults in error-intolerant applications like the automotive industry.
Innovation Solution
A system comprising a main processor and multiple checker processors that execute parallel checker streams, allowing for error detection without requiring each checker processor to match the performance of the main processor, thereby reducing circuit area, power consumption, and wiring complexity, while using checkpoint and memory log circuitry to identify and recover from errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual-core lockstep technique is used for error detection, then error detection capability is improved, but area and power consumption double
Solution Approach 1:
The main processor execution stream is segmented into multiple portions, with each portion assigned to a separate checker processor. This allows error detection to be distributed across multiple smaller processors rather than requiring one large redundant processor, thereby reducing the area overhead while maintaining error detection capability.
Solution Approach 2:
The patent transitions from a single-dimension approach (one main processor with one redundant processor) to a multi-dimensional approach by introducing multiple checker processors that work in parallel. This dimensional expansion allows the system to achieve the same error detection coverage with smaller individual processing units, reducing total area.
2Reliability
If dual-core lockstep technique is used for error detection, then error detection capability is improved, but power consumption doubles
Solution Approach 1:
The error detection workload is segmented and distributed across multiple checker processors, each handling a portion of the main stream. This segmentation allows for more efficient power utilization compared to running a single full-duplicate processor continuously, as each checker processor can be optimized for its specific portion and potentially enter low-power states when idle.
Solution Approach 2:
Instead of creating a complete copy of the main processor (as in dual-core lockstep), the patent creates simplified copies (checker processors) that only need to execute the same instructions on the same inputs to detect errors. These simplified copies consume less power while still providing error detection functionality.
3Reliability
If dual-core lockstep technique is used for error detection, then error detection capability is improved, but wiring complexity increases significantly
Solution Approach 1:
The comparison logic is segmented and distributed to each checker processor rather than requiring a single complex comparison unit. Each checker processor independently compares its portion of the execution stream, eliminating the need for extensive wiring to connect a main processor with a single redundant processor.
Solution Approach 2:
The error detection and comparison functionality is extracted from the main processor and implemented as separate checker processors. This extraction simplifies the wiring requirements by removing the need for complex inter-processor connections, as each checker processor operates semi-independently on its assigned portion.
4Reliability
If dual-core lockstep technique is used for error detection, then error detection capability is improved, but processor size is limited
Solution Approach 1:
The patent segments the error detection task across multiple checker processors, allowing the system to scale to larger main processors by simply adding more checker processors or increasing the parallelism. This segmented approach removes the physical size limitations inherent in dual-core lockstep, where the redundant processor must be physically close to the main processor for wiring purposes.
Solution Approach 2:
The patent moves from a two-processor model to an N-processor model, adding a dimension of scalability. This allows the error detection system to adapt to increasingly large main processors by distributing the checking workload across multiple smaller checker processors, thereby achieving scalability that dual-core lockstep cannot provide.
Data Source
AI summary
An apparatus comprises a main processor to execute a main stream of program instructions, two or more checker processors to execute respective checker streams of program instructions in parallel with each other, the checker streams corresponding to different portions of the main stream executed by the main processor, and error detection circuitry to detect an error when a mismatch is detected between an outcome of a given portion of the main stream executed on the main processor and an outcome of the corresponding checker stream executed on one of the plurality of checker processors. This approach enables high performance main processors 4 to be checked for errors with lower circuit area and power consumption overhead than a dual-core lockstep technique.