Checkerboard DRAM Layout with Variable Gate Width
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Solution Overview
Problem
Conventional checkerboard deep trench DRAM cell arrays face challenges in manufacturing due to narrow bit line contact areas, leading to contact open issues and affected electric properties, especially in 60 nm or sub-60 nm processes, where the aspect ratio is high and the process window for dry etching is small.
Innovation Solution
The proposed checkerboard deep trench DRAM cell array layout features gate conductor lines with narrower widths above deep trench capacitor structures than above active areas, increasing the bit line contact landing area and maintaining sufficient spacer coverage, thus avoiding contact open issues and ensuring stable electric properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the line width of gate conductor lines and the distance between two adjacent gate conductor lines are designed to be as small as 1 feature size, then the integration density is improved, but the bit line contact area becomes too narrow causing contact open issues
Solution Approach 1:
The gate conductor line width is made non-uniform: narrower portions are positioned above deep trench capacitor structures while wider portions are positioned above active areas. This local variation in width provides sufficient contact area width (e.g., 0.65F or 32.5 nm) above active areas while maintaining narrow spacing for high density elsewhere in the cell array.
Solution Approach 2:
The invention introduces width variation along the length of the gate conductor lines, transforming the uniform 1D structure into a structure with dimensional variation. This allows the contact area width to be independently optimized from the overall gate line spacing, resolving the contradiction between density and manufacturability.
2Quantity of substance
If the line width of gate conductor lines is reduced to increase integration, then the manufacturing complexity increases due to high aspect ratio and small process window
Solution Approach 1:
By making the gate conductor line width variable rather than uniform, the invention creates local regions with different dimensional characteristics. The wider portions above active areas provide adequate process window for contact formation, while narrower portions maintain high integration density, thus improving ease of manufacture without sacrificing density.
3Quantity of substance
If the gate conductor line width is uniformly narrow to achieve high density, then the bit line contact area becomes insufficient affecting electric properties
Solution Approach 1:
The gate conductor lines have different widths at different locations: narrower sections above capacitors for density and wider sections above active areas for reliable contact. This ensures sufficient contact area width (e.g., 0.65F) for good electrical connection while maintaining high overall integration density through the variable width design.
Data Source
AI summary
A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of active areas formed in the substrate under the gate conductor lines, alternatively arranged with the deep trench capacitor structures, and electrically connected with an adjacent deep trench capacitor structure. The width of the parts of the gate conductor lines above the deep trench capacitor structures is narrower than that of the parts of the gate conductor lines above the active areas.