Checkerboard MOM Capacitor Array for CMP Uniformity
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Solution Overview
Problem
Conventional array-type Metal-Oxide-Metal (MOM) capacitor designs in semiconductor devices face issues such as chemical-mechanical polishing (CMP) problems like dishing and erosion, capacitance mismatch, and shifts in capacitance from array edge to center, leading to degraded device performance and reliability.
Innovation Solution
An enhanced checkerboard array design is introduced, incorporating both operational and dummy capacitors, which minimizes gradient effects and CMP issues by forming a symmetric pattern of operational and dummy capacitors, and electrically coupling non-adjacent capacitors to improve model accuracy and reduce capacitance mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional array-type MOM capacitor designs are used to increase packing density, then capacitance per unit area increases, but CMP issues such as dishing and erosion worsen
Solution Approach 1:
The patent applies local quality by creating different capacitor types (operational capacitors with signal connections and dummy capacitors without signal connections) within the same array. The dummy capacitors are strategically placed to compensate for CMP-induced variations in specific regions, thereby maintaining uniform capacitance characteristics across the entire array despite local CMP non-uniformity
Solution Approach 2:
The patent introduces asymmetry by implementing a non-uniform distribution of dummy capacitors within the capacitor array. The dummy capacitors are placed in specific patterns that asymmetically compensate for CMP dishing and erosion effects in different regions of the array, rather than using a symmetric uniform distribution
2Quantity of substance
If capacitor array size is increased to improve packing density, then total capacitance increases, but capacitance mismatch across the array worsens
Solution Approach 1:
The patent achieves equipotentiality by ensuring that all capacitors in the array, regardless of their position, have matched capacitance values through the strategic placement of dummy capacitors. This compensation mechanism equalizes the electrical characteristics across the entire array, eliminating potential differences in capacitance that would otherwise arise from position-dependent CMP variations
3Quantity of substance
If capacitor array size is increased to improve packing density, then total capacitance increases, but capacitance shift from array edge to center worsens
Solution Approach 1:
The patent applies local quality by creating different capacitor types (operational capacitors with signal connections and dummy capacitors without signal connections) within the same array. The dummy capacitors are strategically placed to compensate for CMP-induced variations in specific regions, thereby maintaining uniform capacitance characteristics across the entire array despite local CMP non-uniformity
Solution Approach 2:
The patent implements partial or excessive action by adding dummy capacitors that exceed the minimum required for basic array formation. These additional dummy capacitors are specifically positioned to over-compensate for anticipated CMP variations in certain regions, ensuring that even edge-to-center gradients are minimized across large arrays
Data Source
AI summary
Methods of forming semiconductor devices. The method includes forming a capacitor array comprising a plurality of cells in a two-dimensional grid. The step of forming includes forming a plurality of operational capacitors in a first subset of the plurality of cells along a diagonal of the array, the plurality of operational capacitors comprising a first operational capacitor formed in a cell at a first edge of the capacitor array and at a first edge of the diagonal of the capacitor array. The step of forming also includes forming a plurality of dummy patterns about the plurality of operational capacitors in the capacitor array in a second subset of the plurality of cells to achieve symmetry in the grid about the diagonal. The method also includes electrically coupling each one of the plurality of operational capacitors to another one of the plurality of operational capacitors.