Checkerboard Via Formation for Multi-Material IC Alignment
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Solution Overview
Problem
As integrated circuit devices scale down to smaller sizes, the formation of vias becomes challenging due to issues with critical dimensions and alignment, especially when multiple materials are required on the same via contact layer.
Innovation Solution
The use of a sacrificial checkerboard pattern in either an additive or subtractive via formation process to precisely locate and form vias of different materials on the same layer, ensuring accurate critical dimensions and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via formation techniques are used, then via fabrication can be performed, but manufacturing precision and alignment deteriorate as via size scales down
Solution Approach 1:
The patent applies segmentation by dividing the via formation process into distinct stages: forming openings in the dielectric layer, depositing via materials, and using sacrificial layers to define via locations. This segmented approach allows precise control over via dimensions and alignment even as via size scales down to smaller dimensions
Solution Approach 2:
The patent employs preliminary action through the use of sacrificial layers deposited in checkerboard patterns before via material deposition. These sacrificial layers are prepared in advance to precisely define via locations and dimensions, ensuring accurate alignment is achieved before the actual via formation occurs
2Adaptability or versatility
If multiple via materials are required on the same via contact layer, then device functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by enabling different via materials to be deposited in specific locations on the same contact layer. The sacrificial checkerboard pattern allows selective deposition of different via materials at different positions, providing local material variety without requiring complex global process changes
Solution Approach 2:
The patent uses sacrificial layers as intermediary elements that facilitate the deposition of multiple via materials. These sacrificial layers act as mediators that define where each via material should be deposited, simplifying the overall process by providing a clear template for multi-material via formation
Data Source
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AI summary
Techniques are disclosed for forming vias for integrated circuit structures. During an additive via formation process, a dielectric material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is desired to have vias, openings are etched in the dielectric material through the removed regions, and the openings are filled with a first via material. This is then repeated for a second via material. During the subtractive via formation process, a first via material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is not desired to have vias, openings are etched in the first via material through the removed regions. This is then repeated for a second via material.