Checkpoint-Based Equivalence Checking for Circuit Design Models
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Solution Overview
Problem
Current methods for checking functional equivalence between high-level models (HLM) and register-transfer-level (RTL) models of circuit designs face impractical computational resource issues, whether through exhaustive simulation or formal verification, due to the exponential growth of resources required with circuit size.
Innovation Solution
The system determines equivalence by creating checkpoints with characteristic functions and invariants between HLM and RTL models, generating invariant proof problems, and using SAT or SMT solvers to solve these problems, thereby decomposing the complex equivalence checking into smaller, manageable problems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If exhaustive simulation is used to check functional equivalency between HLM and RTL models, then functional equivalency can be guaranteed, but computational resources required become immense and impractical
Solution Approach 1:
The patent divides the complex equivalence checking problem into smaller sub-problems by identifying checkpoints in the HLM and generating corresponding invariant proof problems for each transition between checkpoints. This segmentation allows the verification to be performed on manageable portions rather than exhaustively simulating the entire system, thus reducing computational resource requirements while maintaining verification reliability.
2Reliability
If formal verification techniques are used to prove functional equivalency between two models, then functional equivalency can be proven, but runtime and memory requirements grow exponentially with circuit design size
Solution Approach 1:
The patent segments the formal verification process by identifying specific checkpoints in the HLM and generating invariant proof problems only for transitions between these checkpoints. This approach proves functional equivalency through targeted invariant verification rather than exhaustive formal verification of the entire circuit, thereby reducing runtime and memory requirements that would otherwise grow exponentially with circuit size.
Solution Approach 2:
The patent extracts and focuses verification efforts on critical checkpoints and invariant properties that are sufficient to prove functional equivalency. By taking out only the essential verification points and invariant relationships rather than verifying all possible states and transitions, the method achieves reliable equivalence proof with manageable computational complexity.
3Productivity
If high-level abstraction models are used for circuit design, then design exploration and validation can be performed faster, but ensuring functional equivalency with lower-level models becomes computationally expensive
Solution Approach 1:
The patent maintains the advantages of high-level abstraction for rapid design exploration while enabling efficient equivalence verification by segmenting the verification task into checkpoint-based invariant proof problems. This segmentation allows verification to be performed selectively on critical transitions rather than through resource-intensive exhaustive simulation, thus preserving productivity benefits while reducing verification computational requirements.
Data Source
AI summary
Some embodiments of the present invention provide techniques and systems for determining whether a high-level model (HLM) for a circuit design is equivalent to a register-transfer-level (RTL) model for the circuit design. During operation, a system can identify a set of checkpoints. Each checkpoint can be associated with a characteristic function defined over the states of a finite-state-machine (FSM) representation of the HLM, a characteristic function defined over the states of an FSM representation of the RTL model, and an invariant defined over a set of variables in the HLM and a set of registers in the RTL model. Next, the system can generate a set of invariant proof problems, wherein each invariant proof problem corresponds to a transition between two checkpoints in the set of checkpoints. The system can then determine whether the HLM is equivalent to the RTL model by solving the set of invariant proof problems.