Checksum-Based Coverage Database Merging for Digital Circuit Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for merging coverage databases in integrated circuit design are inefficient, particularly when dealing with complex digital designs where multiple teams work on different blocks and varying configurations, leading to difficulties in obtaining a comprehensive chip-level view due to changes in design hierarchy and functional coverage points.
Innovation Solution
The method involves deriving design and verification checksums from coverage points, which are then used to compare and merge coverage databases from multiple verification runs, allowing for the integration of functional and code coverage data across different simulation runs and design changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If coverage databases from multiple verification runs are merged using traditional methods, then a comprehensive chip-level view is obtained, but the merging process becomes extremely time-consuming and complex due to design hierarchy changes and varying configurations
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing checksums for design elements, coverage points, and coverage data during the verification runs. These checksums are prepared in advance and stored in the coverage databases, enabling rapid comparison during the merging process without requiring complex real-time analysis of design hierarchies and configurations.
Solution Approach 2:
The patent introduces checksums as an intermediary mechanism to facilitate the merging process. Instead of directly comparing complex design hierarchies and coverage data structures, the system uses checksums as intermediate representations that capture the essential characteristics of designs and coverage points, enabling efficient comparison and matching during merging.
2Adaptability or versatility
If multiple design teams work on different blocks with varying configurations and abstraction levels, then design flexibility and parallel development are improved, but merging coverage results becomes difficult due to design hierarchy and functional coverage point changes
Solution Approach 1:
The patent uses checksums as intermediaries that abstract away the complexity of varying design hierarchies and configurations. Each design element, coverage point, and coverage data structure is represented by its checksum, which serves as a configuration-agnostic identifier that enables matching across different design versions and abstraction levels without requiring detailed structural comparison.
Solution Approach 2:
The patent applies parameter changes by computing checksums that capture the essential parameters of design elements and coverage points while being invariant to non-essential changes in design hierarchy and configuration. This allows the merging process to focus on functional equivalence rather than structural identity, accommodating design evolution and configuration variations.
3Measurement precision
If traditional coverage merging methods are used to ensure accurate matching of coverage points across different designs, then measurement accuracy is maintained, but the processing time and computational resources increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-computing checksums for all design elements, coverage points, and coverage data during the verification runs. This preliminary computation stores the essential matching information in advance, allowing the merging process to quickly retrieve and compare checksums rather than performing complex analysis during merging, thus maintaining accuracy while improving throughput.
Solution Approach 2:
The patent uses checksums as simplified copies or representations of the actual design elements and coverage data. Instead of directly comparing complex design structures and coverage point definitions, the system compares their checksum copies, which retain the essential matching information in a compact and efficient form, thereby maintaining accuracy while reducing computational overhead.
Data Source
AI summary
A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment, design and verification checksums are calculated for instances of a desired module. The design and verification checksums may be used to further derive hierarchical design and functional checksums. In another embodiment, these checksums are used to merge multiple databases produced by verification runs. In a further embodiment a computing apparatus is provided. The computing apparatus is configured to merge multiple verification databases.