Checksum Circuit Modulo 65536 Correction Hardware
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Solution Overview
Problem
Existing checksum algorithms that use non-power of 2 modulo calculations, such as the Adler-32 algorithm, are difficult to implement efficiently in hardware due to the need for numerous multiplexers and complex modulo operations, leading to increased circuit area and reduced speed.
Innovation Solution
A hardware checksum circuit and software implementation that optimizes the Adler-32 checksum calculation by performing modulo operations after summing, reducing the need for multiplexers and using a modulo 65,536 calculation with correction to achieve modulo 65,521, thereby minimizing hardware requirements and improving speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If non-power of 2 modulo calculations are implemented in hardware, then checksum accuracy is maintained, but circuit area increases and speed decreases
Solution Approach 1:
The patent changes the modulo parameter from 65,521 (non-power of 2) to 65,536 (power of 2), which allows using simple bitwise AND operations instead of complex division-based modulo operations. This parameter change maintains checksum accuracy while dramatically reducing hardware complexity and increasing speed.
Solution Approach 2:
The patent uses a correction value approach where instead of implementing complex modulo 65,521 hardware, it uses a simpler modulo 65,536 hardware combined with a correction step. The correction value is pre-calculated and applied only when necessary, effectively replacing expensive hardware with a cheaper simpler hardware plus a minor correction step.
2Measurement precision
If non-power of 2 modulo calculations are implemented in hardware, then checksum accuracy is maintained, but calculation speed decreases
Solution Approach 1:
The patent changes the modulo parameter from 65,521 (non-power of 2) to 65,536 (power of 2), which allows using simple bitwise AND operations instead of complex division-based modulo operations. This parameter change maintains checksum accuracy while dramatically reducing hardware complexity and increasing speed.
Solution Approach 2:
The patent uses a correction value approach where instead of implementing complex modulo 65,521 hardware, it uses a simpler modulo 65,536 hardware combined with a correction step. The correction value is pre-calculated and applied only when necessary, effectively replacing expensive hardware with a cheaper simpler hardware plus a minor correction step.
3Measurement precision
If modulo operations are performed during each summing operation, then checksum accuracy is maintained, but hardware requirements increase
Solution Approach 1:
The patent performs the modulo operation only after all summing operations are complete, rather than during each summing operation. This preliminary action approach reduces the number of modulo operations from many to just one, significantly reducing hardware requirements while maintaining accuracy through the use of a power of 2 modulo base.
Solution Approach 2:
The patent changes the modulo parameter from 65,521 (non-power of 2) to 65,536 (power of 2), which allows using simple bitwise AND operations instead of complex division-based modulo operations. This parameter change maintains checksum accuracy while dramatically reducing hardware complexity and increasing speed.
Data Source
AI summary
A hardware circuit computes a checksum using a technique such as the Adler-32 checksum algorithm. The hardware circuit may include one or more serially-connected chains of adders followed by a modulus circuit. The modulus circuit produces a modulus value in N, where N is not an integer power of 2. In some examples, N is 65,521. In some examples, the modulus circuit may produce a modulus value modulo 216 and then correct that value to modulo N. In other examples, the modulus circuit may include selection logic that selects an appropriate integer multiple of 65,521 to determine the modulo 65,521 result directly.