Chemical Etching Exposes TSV Tips Without Mechanical Damage
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Solution Overview
Problem
Conventional via-first TSV processes damage, scratch, or crack TSV tips during backgrinding, leading to electrical leakage and reduced minority carrier lifetimes due to mechanical contact and smearing of conductive filler material, which degrades IC performance and reliability.
Innovation Solution
Modify the backgrinding process to only partially thin the wafer, leaving a protective substrate layer, and then use chemical etching to expose the TSV tips, avoiding direct mechanical contact and minimizing damage to the dielectric liner and conductive filler material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If backgrinding is used to thin the wafer to expose the TSV tip, then the TSV tip can be accessed for electrical connection, but the TSV tip suffers mechanical damage, scratching and cracking
Solution Approach 1:
The patent replaces the mechanical backgrinding process with a chemical etching process to expose the TSV tip. Instead of using abrasive mechanical forces that cause damage, the chemical etchant selectively removes the substrate material around the TSV tip through chemical reactions, thereby exposing the TSV tip without mechanical contact or damage.
Solution Approach 2:
The patent changes the fundamental parameter of the material removal process from mechanical (backgrinding) to chemical (etching). This parameter change allows the TSV tip to be exposed through a non-mechanical process that does not impose mechanical stress, scratching, or cracking forces on the delicate TSV tip structure.
2Manufacturing precision
If backgrinding is used to reach the TSV tip, then substrate thinning is achieved, but electrical leakage paths are created between TSV and substrate
Solution Approach 1:
The patent substitutes chemical etching for mechanical backgrinding to eliminate the creation of electrical leakage paths. The chemical process cleanly removes substrate material without creating the mechanical damage and conductive debris that backgrinding produces, thereby preventing electrical leakage between the TSV and substrate.
Solution Approach 2:
The patent converts the potential harm of aggressive substrate removal into a benefit by using selective chemical etching. The chemical etchant selectively removes only the substrate material while leaving the TSV tip and its protective layers intact, thereby achieving the necessary substrate thinning without creating the harmful electrical leakage paths that result from mechanical backgrinding.
3Reliability
If conventional CMP and chemical etch are used after backgrinding, then some damage is reduced, but residual damage and scratching remain in the dielectric liner and conductive filler material
Solution Approach 1:
The patent inverts the conventional process sequence by performing chemical etching before any polishing or finishing steps. Instead of backgrinding first and then attempting to repair damage with CMP and etching, the patent uses chemical etching as the primary exposure method from the outset, thereby preventing the creation of residual damage that would require subsequent repair steps.
Solution Approach 2:
The patent replaces the mechanical CMP process with a chemical etching approach for exposing the TSV tip. This substitution eliminates the mechanical scratching and rubbing that CMP causes to the dielectric liner and conductive filler material, thereby achieving TSV tip exposure without residual mechanical damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces mechanical damage and smearing, improving electrical isolation between TSVs and the substrate, thereby enhancing IC performance and reliability by forming protruding integral TSV tips that reduce electrical leakage.
Implementation Method 1
use chemical etching to expose the TSV tips, avoiding direct mechanical contact and minimizing damage to the dielectric liner and conductive filler material
Data Source
AI summary
A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.