Chessboard Switchbox Layout for FPGA Routing With Less Chip Area
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Solution Overview
Problem
The existing connection architectures in programmable logic devices, such as FPGAs, require excessive resources for connection elements, leading to inefficiencies and increased chip area, while maintaining good routeability remains a challenge.
Innovation Solution
Implementing a reduced switchbox allocation where only 30-70% of grid coordinates have switchboxes, arranged in a chessboard-like pattern with alternating positions and sizes, and connecting them along coordinate axes and diagonals to enable direction changes without switchboxes at every intersection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If switchboxes are assigned to every CLB in Island-Style topology, then routeability is maintained, but chip area and connection effort increase significantly
Solution Approach 1:
The patent divides the FPGA into multiple regions, each containing a reduced number of switchboxes (only 30-70% of CLBs have switchboxes in their region). This segmentation allows routeability to be maintained within each region while reducing the overall number of switchboxes needed across the entire device, thereby reducing chip area.
Solution Approach 2:
The patent introduces a new dimensional approach by allowing signals to change direction not only at switchbox locations but also at CLB locations. This adds a new dimension to the routing paradigm, enabling efficient routing with fewer switchboxes by utilizing CLB-based direction changes.
2Adaptability or versatility
If switchboxes are assigned to every CLB, then signal routing capability is improved, but connection effort and complexity increase
Solution Approach 1:
The patent makes CLBs multi-functional by enabling them to serve both as logic elements and as routing nodes for direction changes. This universality allows the same CLB structure to perform multiple functions, reducing the need for dedicated switchboxes and thereby reducing connection effort and device complexity.
Solution Approach 2:
The patent applies partial action by providing switchboxes for only 30-70% of CLBs rather than all CLBs. This partial coverage is sufficient to maintain routing capability while significantly reducing the number of connection elements and overall device complexity.
3Area of stationary object
If switchboxes are reduced to 30-70% of CLBs, then chip area is reduced, but routeability may be compromised
Solution Approach 1:
The patent performs preliminary routing planning that anticipates signal paths and directs them through regions with switchboxes before they are needed. This preliminary action ensures that even with reduced switchbox density, routing capability is maintained by pre-positioning switchboxes strategically in each region.
Solution Approach 2:
The patent uses CLBs as intermediary routing nodes between switchboxes. When switchboxes are not available at every CLB, the CLB itself acts as an intermediary that can change signal direction, effectively mediating the routing function and maintaining routeability with fewer switchboxes.
Data Source
AI summary
Switchboxes are especially used in integrated circuits with programmable logic (e.g. FPGAs). They are used to establish configurable signal paths between logic blocks. It is especially important to use an efficient structure, i.e. a structure whose chip area is as small as possible and which is able to realize short and fast signal paths. The task of the present invention is to significantly reduce the effort for the interconnection structures while still maintaining good routeability. This is achieved by the fact that there is no longer a switchbox (SB) on each coordinate position. It is particularly advantageous to arrange the SBs in a chessboard-like manner and also to use two SBs of different sizes which are arranged in a superordinate chessboard structure.