Variable-Speed Chien Search Circuit for Adaptive ECC Decoding
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Solution Overview
Problem
Large codewords with more parity bits require complex algorithms and substantial computing resources to reduce bit error rates, leading to inefficient use of resources due to the need for exhaustive searches in Chien search circuits, which are designed for worst-case scenarios but often encounter fewer errors in practice.
Innovation Solution
A variable speed Chien search architecture that determines whether to find error locations in a single pass or multiple passes based on the degree of the error locator polynomial, optimizing resource usage by adapting to the actual number of errors present.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a Chien search circuit is designed to find all possible roots for worst-case scenarios, then error location accuracy is improved, but computing resources and circuit complexity increase substantially
Solution Approach 1:
The Chien search circuit implements a dynamic search depth parameter that can be adjusted based on the actual error conditions detected in the received signal. Instead of always performing exhaustive searches through all possible roots, the circuit adaptively limits the search depth when fewer errors are present, thereby reducing computing resources and circuit complexity while maintaining accurate error location when needed
Solution Approach 2:
The invention changes the operational parameters of the Chien search circuit by introducing a variable search depth parameter. This parameter is modified based on the degree of the error locator polynomial and the actual error conditions, allowing the circuit to operate efficiently in both low-error and high-error scenarios without requiring full worst-case complexity in all situations
2Reliability
If a Chien search circuit is designed for worst-case scenarios, then reliability is improved, but processing time increases due to exhaustive searches
Solution Approach 1:
The circuit dynamically adjusts the number of search passes and search depth based on the actual error conditions detected. When the degree of the error locator polynomial indicates fewer errors, the circuit performs fewer passes with reduced search depth, significantly reducing decoding time while maintaining reliable error correction. When more errors are detected, the circuit automatically increases the search effort to ensure all error locations are found
3Reliability
If large codewords with more parity bits are used, then bit error rate reduction is improved, but computing resources required increase
Solution Approach 1:
The variable speed Chien search architecture dynamically adapts the computing resources allocated to error correction based on the actual error conditions in the received signal. By adjusting the search depth and number of passes according to the degree of the error locator polynomial, the system efficiently handles both large and small error scenarios, reducing the average computing resource consumption while maintaining the bit error rate protection provided by large codewords with more parity bits
Data Source
AI summary
Examples are disclosed for using or designing Chien search circuitry to locate errors for error correction code (ECC) encoded data. In some examples, an error locator polynomial (ELP) may be received that indicates a number of possible error locations for ECC encoded data. Chien search circuitry may be designed such that error locations are found based on the received ELP within one or more passes through the search circuitry. The design of the Chien search circuitry to accommodate both an average expected number of error locations for received ELPs and a worst case number of error locations for received ELPs. Other examples are described and claimed.