Chien Search Clock Gating for Low-Power Memory Error Detection
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Solution Overview
Problem
Semiconductor storage devices with increasing storage capacity face high consumption current issues due to error detecting devices, necessitating a low-consumption error detecting solution.
Innovation Solution
The error detecting device incorporates a Chien search processor with a clock controller, buffer, and polynomial generator that dynamically controls clock signals based on sigma values and estimated error counts to reduce unnecessary current consumption, optimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If storage capacity of semiconductor storage device is increased, then error detecting device consumes more current
Solution Approach 1:
The patent applies dynamics by making the clock signal operation dynamic rather than static. The clock controller dynamically adjusts the clock signal based on whether sigma values are zero or non-zero, allowing the error detecting device to adapt its operation mode (active or idle) according to the actual data conditions, thereby reducing unnecessary current consumption while maintaining storage capacity
Solution Approach 2:
The patent changes the operational parameter (clock signal state) based on the sigma value parameter. When sigma values are determined to be zero, the system changes the clock signal parameter to a stopped state, reducing power consumption. This parameter change approach allows the device to maintain high storage capacity while consuming less current during operations where error detection is not needed
2Reliability
If error detecting device operates continuously, then error detection reliability is maintained, but power consumption increases
Solution Approach 1:
The patent implements periodic action by alternating between active clock operation and stopped clock state. The clock controller periodically activates the clock signal only when sigma values indicate potential errors (non-zero), and stops the clock when sigma values are zero, creating a periodic on-off pattern that maintains detection reliability while reducing overall power consumption
Solution Approach 2:
The patent extracts and removes the unnecessary clock operation from the system. By identifying that certain sigma values are zero and extracting the redundant clock signaling during these periods, the system eliminates wasted power consumption while preserving the essential error detection functionality when actually needed
Data Source
AI summary
According to one embodiment, an error detecting device includes a syndrome processor, an error locator polynomial generator, and a search processor. The syndrome processor is configured to generate syndrome values based on received data. The error locator polynomial generator is configured to generate coefficients for an error locator polynomial based on the syndrome values. The search processor configured to detect an error location by calculating a root of the error locator polynomial. The search processor has a clock controller, a buffer, a polynomial generator, and a first judging module. The clock controller is configured to output or stop a clock signal according to at least one of the coefficients. The buffer is configured to drive the clock signal outputted form the clock controller. The polynomial generator is configured to calculate a part of the error locator polynomial in synchronization with the clock signal driven by the buffer.