Chien Search Circuit Layout for Parallel ECC With Less Wiring
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Solution Overview
Problem
In high-capacity memory devices like NAND flash memory, the increasing error rate due to data retention issues necessitates efficient error check and correction mechanisms, particularly in parallel processing scenarios where existing Chien search circuits require extensive wiring and increased size, hindering performance.
Innovation Solution
The proposed solution involves a Chien search unit with a matrix arrangement of Chien search circuits that calculate error locations using Galois field elements, where a first bit stream and a second bit stream are multiplied by predetermined values and input to the circuits, reducing the need for extensive wiring by providing signals in row and column directions, allowing for efficient error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of Chien search circuits is increased to process multiple bits in parallel, then the error correction capability is improved, but the number of wirings and circuit size increase
Solution Approach 1:
Multiple Chien search circuits are merged into a single circuit by time-multiplexing the error location search process. The circuit processes multiple error locations sequentially by updating the substituted value α according to the error location number, rather than requiring separate circuits for each error location. This combining approach maintains error correction capability while significantly reducing circuit size and wiring complexity.
Solution Approach 2:
The Chien search circuit employs dynamic operation where the substituted value α is updated sequentially based on the error location number. The circuit dynamically adjusts its operation mode: when no error is detected at current location, it proceeds to the next location by updating α; when an error is detected, it performs correction and continues. This dynamic adaptation allows a single circuit to handle multiple error locations that would otherwise require multiple static circuits.
2Productivity
If the number of Chien search circuits is increased to process multiple bits in parallel, then the processing speed is improved, but the number of wirings increases
Solution Approach 1:
The patent merges multiple wiring paths into a single shared wiring structure. Instead of providing separate signal lines from each multiplier to each Chien search circuit, the invention uses a common wiring path that is time-multiplexed across different error locations. The control unit manages this shared wiring by sequentially enabling different error locations to use the same physical connections, thereby reducing the total number of wirings while maintaining parallel processing capability through time-multiplexing.
Solution Approach 2:
The Chien search circuit operates periodically by cycling through different error locations in sequence. The control unit generates periodic control signals that enable the circuit to process error locations one after another in a systematic manner. This periodic operation allows a single circuit to achieve the functional equivalent of multiple parallel circuits, maintaining processing speed while reducing wiring complexity through time-multiplexed resource sharing.
Data Source
AI summary
An error check and correction circuit includes a Chien search unit. The Chien search unit includes a calculation circuit and a plurality of Chien search circuits. The calculation circuit is configured to calculate a first bit stream by multiplying a value of (n−k) bits by a plurality of elements and a second bit stream by multiplying a value of k bits by the plurality of elements. The plurality of Chien search circuits configured to calculate the element by connecting the first bit stream and the second bit stream, and substitute the calculated element into the error correction search equation.