Processor Chip Address Computation for Flexible Tensor Data Access
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Solution Overview
Problem
Existing processor chips face inefficiencies due to rigid data access modes that limit flexibility and computational efficiency, particularly in neural network computations, leading to high power consumption and inflexible strategies.
Innovation Solution
A processor chip design that allows flexible data access through a storage control unit with an address computing module, which computes addresses in memory loops based on software-configured parameters, enabling flexible reading of data elements without being limited by storage order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a customized pipeline is used to achieve high efficiency, then computational efficiency is improved, but flexibility is sacrificed
Solution Approach 1:
The patent implements a dynamic data pipeline where the address computing module can switch between different access modes (sequential, strided, random) based on software-configured parameters. This allows the system to adapt its data access strategy dynamically without requiring hardware modification, resolving the contradiction between efficiency and flexibility by making the pipeline configurable rather than fixed.
Solution Approach 2:
The system uses software-configured parameters to control the address computing behavior, allowing different access patterns (sequential access, strided access, random access) to be selected by changing parameters rather than hardware structure. This enables the same hardware to achieve different efficiency levels for different workloads, maintaining both high efficiency and flexibility.
2Speed
If a large on-chip buffer is added to solve bandwidth and latency problems, then data access speed is improved, but hardware cost and complexity increase
Solution Approach 1:
The patent replaces the mechanical approach of adding more physical buffer memory with a computational approach using an address computing module. Instead of increasing hardware capacity to improve speed, the system uses software-configured address computation to optimize data access patterns, reducing latency through intelligent addressing rather than through additional buffering hardware.
Solution Approach 2:
The address computing module acts as an intermediary between the storage control unit and the computing unit. It translates software access requirements into optimized address sequences, mediating the data flow to reduce latency without requiring large on-chip buffers. This intermediary layer enables efficient data access through computation rather than through hardware expansion.
3Ease of operation
If hardware-coupled computation and storage are used, then access mode is simplified, but software control flexibility is lost
Solution Approach 1:
The address computing module serves as an intermediary layer that receives software control parameters and translates them into hardware-executable address sequences. This intermediary enables software to control the computation-storage interaction flexibly while maintaining the simplicity of hardware execution, as the software only needs to configure parameters rather than directly control hardware operations.
Solution Approach 2:
The address computing module automatically generates the address sequence based on software-configured parameters without requiring direct software intervention in each access operation. Once configured, the system self-manages the address computation and data access, maintaining hardware simplicity while enabling software flexibility through parameter configuration.
Data Source
AI summary
A processor chip, a method for flexibly accessing data in the processor chip, an electronic device, and a non-transitory storage medium are provided. The chip includes: a memory, configured to store read-in tensor data from outside the processor chip; a storage control unit, configured to control reading elements from the memory according to the tensor operation of the operator to send the elements to a computing unit, where the storage control unit includes an address computing module, and the address computing module computes addresses in the memory in one-layer read loop or multi-layer read loop nest according to the parameter configured that is received by the interface, so as to read the elements from computed addresses and send the elements to the computing unit; and the computing unit, configured to perform the tensor operation of the operator by using the elements received.