Chip Address Translation for High-Speed Data Transfer
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Solution Overview
Problem
The existing methods for increasing processing speed by dividing circuits into multiple chips and using high-speed serial interfaces like PCI Express require additional switches, leading to increased costs.
Innovation Solution
An information processing apparatus with multiple chips connected in series, where each chip includes a receiving unit, a register for address translation, a determination unit, an address translation unit, a controller unit, and a transmission unit, allowing for address translation and efficient data transfer between chips without the need for additional switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If PCI Express switches are added to connect multiple image processing units to the PCI Express interface, then high-speed data transfer between chips is achieved, but the cost is increased
Solution Approach 1:
The patent introduces an address translation unit as an intermediary component within each chip to translate address information between different address spaces. This mediator enables direct peer-to-peer data transfer between chips without requiring external PCI Express switches, thereby achieving high-speed data transfer while reducing system cost by eliminating the need for additional switch hardware.
Solution Approach 2:
The patent divides the address space into multiple segments, with each chip having its own address translation unit that manages local address space segmentation. This segmentation allows each chip to independently translate addresses to the destination chip's address space, enabling direct communication without centralized switching infrastructure and reducing overall system cost.
2Productivity
If circuits are divided into multiple chips to increase processing speed, then parallel processing capability is improved, but device complexity is increased
Solution Approach 1:
The patent implements a universal address translation unit that can handle multiple functions: translating addresses to local chip memory, translating addresses to remote chips, and managing different address spaces. This multi-functional component simplifies the overall system architecture by providing a standardized mechanism for all inter-chip communications, reducing the complexity that would otherwise arise from having specialized communication paths for each function.
Solution Approach 2:
Each chip is equipped with its own address translation unit that autonomously translates address information without requiring external assistance from PCI Express switches or centralized controllers. This self-service capability allows each chip to independently manage its own address translation needs, simplifying the system architecture by eliminating the need for complex centralized address management infrastructure.
Data Source
AI summary
An information processing apparatus includes a first, second, and third chips connected in series. The second chip includes a receiving unit, a register, a determination unit, an address translation unit, a controller unit, and a transmission unit. The receiving unit receives data and address information from the first chip. The determination unit determines whether the received address information corresponds to an address translation area based on address translation information set to the register. The address translation unit outputs translated address information to an internal bus. The controller unit controls to store data to which address information corresponding to an address area set for the second chip is attached. The transmission unit transmits to the third chip data to which address information is attached. The address translation unit translates address information corresponding to an address area set for the second chip into an address destination in the second chip.